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  document no. u15947ej2v0ud00 (2nd edition) date published september 2003 n cp(k) printed in japan ? pd780143 pd780143(a) pd780143(a1) pd780143(a2) pd780144 pd780144(a) pd780144(a1) pd780144(a2) pd780146 pd780146(a) pd780146(a1) pd780146(a2) pd780148 pd780148(a) pd780148(a1) pd780148(a2) pd78f0148 pd78f0148(a) pd78f0148(a1) 78k0/kf1 8-bit single-chip microcontrollers user?s manual
user?s manual u15947ej2v0ud 2 [memo]
user?s manual u15947ej2v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. windows and windows nt are either registered trademarks or trademar ks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. tron is an abbreviati on of the realtime operating system nucleus. itron is an abbreviation of industrial tron.
user?s manual u15947ej2v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of april, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ?
user?s manual u15947ej2v0ud 5 regional information ? ? ? ? ? ?
user?s manual u15947ej2v0ud 6 major revisions in this edition (1/3) page description addition of products ? ? ? ? ?
user?s manual u15947ej2v0ud 7 major revisions in this edition (2/3) page description p.148 addition of cautions 2 and 3 to figure 6-6 format of oscillation stabilization time counter status register (ostc) pp.150 to 152 modification of figure 6-8 examples of external circuit of x1 oscillator, figure 6-9 examples of external circuit of subsystem clock oscillator, and figure 6-10 examples of incorrect resonator connection p.157 modification of notes 4 and 5 in figure 6-13 status transition diagram (2) p.159 modification of note 4 and illustration in figure 6-13 status transition diagram (4) p.160 modification of table 6-3 relationship between operation clocks in each operation status p.163 modification of note in figure 6-14 switching from ring-osc clock to x1 input clock (flowchart) p.165 addition of note to figure 6-16 switching from x1 input clock to subsystem clock (flowchart) p.168 revision of chapter 7 16-bit timer/event counters 00 and 01 p.212 revision of chapter 8 8-bit timer/event counters 50 and 51 p.230 revision of chapter 9 8-bit timers h0 and h1 p.255 modification of figure 10-1 watch timer block diagram p.261 addition of figure 10-4 example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) p.272 modification of figure 12-1 block diagram of clock output/buzzer output controller p.277 revision of chapter 13 a/d converter p.299 revision of chapter 14 serial interface uart0 p.320 revision of chapter 15 serial interface uart6 p.358 revision of chapter 16 serial interfaces csi10 and csi11 p.378 revision of chapter 17 serial interface csia0 p.418 revision of chapter 18 multiplier/divider pp.429, 430 addition of note to intvli, poc, and lvi in table 19-1 interrupt source list p.433 addition of note 2 to table 19-2 flags corresponding to interrupt request sources p.434 addition of caution 2 to figure 19-2 format of interrupt request flag registers (if0l, if0h, if1l, if1h) p.437 addition of caution to table 19-3 ports corresponding to egpn and egnn p.442 addition of software interrupt request item to table 19-5 relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing p.446 modification of figure 20-1 block diagram of key interrupt p.448 modification of table 21-1 relationship between halt mode, stop mode, and clock in old edition to table 21-1 relationship between operation clocks in each operation status p.450 addition of cautions 2 and 3 to figure 21-1 format of oscillation stabilization time counter status register (ostc) p.452 modification of table 21-1 operating statuses in halt mode p.456 addition of (3) when subsystem clock is used as cpu clock to figure 21-4 halt mode release by reset input p.457 modification of the following items in table 21-4 operating statuses in stop mode ? ?
user?s manual u15947ej2v0ud 8 major revisions in this edition (3/3) page description p.467 modification of mask flag register 1h (mk1h) in table 22-1 hardware statuses after reset acknowledgment p.469 modification of figure 23-1 block diagram of clock monitor p.471 addition of operation mode to table 23-2 operation status of clock monitor (when clme = 1) pp.474, 475 addition of (6) clock monitor status after x1 input clock oscillation is stopped by software and (7) clock monitor status after ring-osc clock oscillation is stopped by software to figure 23-3 timing of clock monitor p.476 addition of note to description in 24.1 functions of power-on-clear circuit p.477 modification of figure 24-1 block diagram of power-on-clear circuit p.480 addition of note to description in 25.1 functions of low-voltage detector p.480 modification of figure 25-1 block diagram of low-voltage detector p.482 modification of note 5 in figure 25-2 format of low-voltage detection register (lvim) p.483 addition of note 2 and caution to figure 25-3 format of low-voltage detection level selection register (lvis) pp.485, 487 modification of figure 25-4 timing of low-voltage detector internal reset signal generation and figure 25-5 timing of low-voltage detector interrupt signal generation p.491 partial modification of description of (2) when used as interrupt under in 25.5 cautions for low-voltage detector p.492 revision of chapter 26 regulator p.494 addition of note to chapter 27 mask options p.495 revision of chapter 28
user?s manual u15947ej2v0ud 9 introduction readers this manual is intended for user engineers who wish to understand the functions of the 78k0/kf1 and design and develop applicatio n systems and programs for these devices. the target products are as follows. 78k0/kf1: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
user?s manual u15947ej2v0ud 10 ? ?
user?s manual u15947ej2v0ud 11 documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78k0k1-et in-circuit emulator to be prepared ie-780148-ns-em1 emulation board to be prepared documents related to fl ash memory programming document name document no. pg-fp3 flash memory programmer user?s manual u13502e pg-fp4 flash memory programmer user?s manual u15260e other documents document name document no. semiconductor selection guide ? ?
user?s manual u15947ej2v0ud 12 contents chapter 1 outline........................................................................................................... .................. 33 1.1 features ....................................................................................................................... .............. 33 1.2 applications ................................................................................................................... ........... 34 1.3 ordering information ........................................................................................................... ..... 35 1.4 pin configuration (top view)................................................................................................... 38 1.5 k1 family lineup ............................................................................................................... ....... 40 1.5.1 78k0/kx1 prod uct lin eup ........................................................................................................ ...... 40 1.5.2 v850es/kx1 pr oduct li neup ...................................................................................................... ... 42 1.6 block diagram.................................................................................................................. ......... 44 1.7 outline of functions ........................................................................................................... ...... 45 chapter 2 pin functions .................................................................................................... ........... 47 2.1 pin function list.............................................................................................................. ......... 47 2.2 description of pin functions ................................................................................................... 51 2.2.1 p00 to p06 (port 0) ............................................................................................................ ........... 51 2.2.2 p10 to p17 (port 1) ............................................................................................................ ........... 52 2.2.3 p20 to p27 (port 2) ............................................................................................................ ........... 52 2.2.4 p30 to p33 (port 3) ............................................................................................................ ........... 53 2.2.5 p40 to p47 (port 4) ............................................................................................................ ........... 53 2.2.6 p50 to p57 (port 5) ............................................................................................................ ........... 53 2.2.7 p60 to p67 (port 6) ............................................................................................................ ........... 54 2.2.8 p70 to p77 (port 7) ............................................................................................................ ........... 54 2.2.9 p120 (por t 12) ................................................................................................................. ............. 54 2.2.10 p130 (por t 13) ................................................................................................................. ............. 54 2.2.11 p140 to p145 (port 14) ......................................................................................................... ........ 55 2.2.12 av ref ............................................................................................................................... ............. 55 2.2.13 av ss ............................................................................................................................... .............. 55 2.2.14 reset .......................................................................................................................... ............... 56 2.2.15 regc........................................................................................................................... ................ 56 2.2.16 x1 and x2...................................................................................................................... ............... 56 2.2.17 xt1 and xt2 .................................................................................................................... ............ 56 2.2.18 v dd and ev dd ............................................................................................................................... 56 2.2.19 v ss and ev ss ............................................................................................................................... .56 2.2.20 v pp (flash memory ve rsions on ly) ................................................................................................. 5 6 2.2.21 ic (mask rom vers ions only).................................................................................................... ... 56 2.3 pin i/o circuits and recommende d connection of unused pins........................................ 57 chapter 3 cpu architecture ................................................................................................. ..... 61 3.1 memory space................................................................................................................... ........ 61 3.1.1 internal program memory space.................................................................................................. .67 3.1.2 internal data memory space ..................................................................................................... .... 68 3.1.3 special function r egister (s fr) area ........................................................................................... .68 3.1.4 data memory addre ssing ......................................................................................................... .... 69
user?s manual u15947ej2v0ud 13 3.2 processor registers............................................................................................................ ..... 74 3.2.1 control re gisters.............................................................................................................. ..............74 3.2.2 general-purpose regist ers ...................................................................................................... ......78 3.2.3 special function registers (sfrs).............................................................................................. ....79 3.3 instruction address addressing...................................... ....................................................... 84 3.3.1 relative ad dressi ng............................................................................................................ ...........84 3.3.2 immediate ad dressi ng........................................................................................................... ........85 3.3.3 table indirect addre ssing ...................................................................................................... ........86 3.3.4 register addressi ng ............................................................................................................ ..........86 3.4 operand address addressing....................... .......................................................................... 87 3.4.1 implied addr essi ng ............................................................................................................. ...........87 3.4.2 register addressi ng ............................................................................................................ ..........88 3.4.3 direct addr essing .............................................................................................................. ............89 3.4.4 short direct addre ssing ........................................................................................................ .........90 3.4.5 special function regist er (sfr) addr essing ...................................................................................91 3.4.6 register indire ct addre ssing................................................................................................... .......92 3.4.7 based addr essing ............................................................................................................... ..........93 3.4.8 based indexed addres sing....................................................................................................... .....94 3.4.9 stack addr essing............................................................................................................... ............95 chapter 4 port functions ................................................................................................... ........ 96 4.1 port functions ................................................................................................................. ......... 96 4.2 port configuratio n ............................................................................................................. ....... 98 4.2.1 port 0 ......................................................................................................................... ...................99 4.2.2 port 1 ......................................................................................................................... .................103 4.2.3 port 2 ......................................................................................................................... .................108 4.2.4 port 3 ......................................................................................................................... .................109 4.2.5 port 4 ......................................................................................................................... .................111 4.2.6 port 5 ......................................................................................................................... .................112 4.2.7 port 6 ......................................................................................................................... .................113 4.2.8 port 7 ......................................................................................................................... .................116 4.2.9 port 12 ........................................................................................................................ ................117 4.2.10 port 13 ........................................................................................................................ ................118 4.2.11 port 14 ........................................................................................................................ ................119 4.3 registers controlling port function.. ................................................................................... 123 4.4 port function operations ............................................. ......................................................... 1 28 4.4.1 writing to i/o port ............................................................................................................ ............128 4.4.2 reading from i/o port.......................................................................................................... ........128 4.4.3 operations on i/o por t......................................................................................................... ........128 chapter 5 external bus interface ...................................................................................... 129 5.1 external bus interface......................................................................................................... ... 129 5.2 registers controlling external bus in terface...................................................................... 132 5.3 external bus interface function timi ng .............................................................................. 135 5.4 example of connection with memory.......................... ......................................................... 140
user?s manual u15947ej2v0ud 14 chapter 6 clock generator .................................................................................................. .. 141 6.1 functions of clock generator ........................................... .................................................... 141 6.2 configuration of clock generator. ........................................................................................ 141 6.3 registers controlling clock generator ........................ ........................................................ 143 6.4 system clock oscillator........................................................................................................ . 150 6.4.1 x1 osc illat or.................................................................................................................. .............. 150 6.4.2 subsystem clo ck oscilla tor ..................................................................................................... .... 150 6.4.3 when subsystem clo ck is not used ............................................................................................ 153 6.4.4 ring-osc os cillator............................................................................................................ ........ 153 6.4.5 presca ler ...................................................................................................................... .............. 153 6.5 clock generator operat ion .................................................................................................... 15 4 6.6 time required to switch between ring-osc clo ck and x1 input clock ......................... 161 6.7 time required for cpu clock switchover ................... ........................................................ 162 6.8 clock switching flowchart and register setting ...... .......................................................... 163 6.8.1 switching from ring-osc clo ck to x1 input cloc k ...................................................................... 163 6.8.2 switching from x1 input cl ock to ring-os c cloc k ...................................................................... 164 6.8.3 switching from x1 input cl ock to subsyst em cloc k ..................................................................... 165 6.8.4 switching from subsystem cl ock to x1 i nput cloc k ..................................................................... 166 6.8.5 register settings.............................................................................................................. ........... 167 chapter 7 16-bit timer/event counters 00 and 01......................................................... 168 7.1 functions of 16-bit timer/e vent counters 00 and 01 .............. ........................................... 168 7.2 configuration of 16-bit timer/event counters 00 a nd 01................................................... 169 7.3 registers controlling 16-bit ti mer/event counters 00 and 01 ..... ..................................... 174 7.4 operation of 16-bit timer/event counters 00 and 01 ......................................................... 185 7.4.1 interval time r operat ion....................................................................................................... ........ 185 7.4.2 ppg output op eratio ns .......................................................................................................... ..... 188 7.4.3 pulse width measur ement opera tions ........................................................................................ 191 7.4.4 external event c ounter oper ation............................................................................................... . 199 7.4.5 square-wave out put operat ion ................................................................................................... 202 7.4.6 one-shot pulse out put operation ................................................................................................ 204 7.5 cautions for 16-bit timer/event counters 00 and 01 .......................................................... 209 chapter 8 8-bit timer/event counters 50 and 51........................................................... 212 8.1 functions of 8-bit timer/event coun ters 50 and 51 ........................................................... 212 8.2 configuration of 8-bit timer/even t counters 50 and 51................ ..................................... 214 8.3 registers controlling 8- bit timer/event c ounters 50 and 51 ............................................ 216 8.4 operations of 8-bit timer/event counters 50 and 51 ......................................................... 221 8.4.1 operation as interval timer .............................................................................................. ........... 221 8.4.2 operation as exter nal event counter .......................................................................................... 22 3 8.4.3 square-wave out put operat ion ................................................................................................... 224 8.4.4 pwm output operatio n........................................................................................................... ..... 225 8.5 cautions for 8-bit timer/event c ounters 50 and 51............................................................ 229
user?s manual u15947ej2v0ud 15 chapter 9 8-bit timers h0 and h1 ........................................................................................ .. 230 9.1 functions of 8-bit timers h0 and h1 .................................................................................... 230 9.2 configuration of 8-bit timers h0 and h1 ............................................................................. 230 9.3 registers controlling 8-bit timers h0 and h1 ........ ............................................................ 234 9.4 operation of 8-bit timers h0 and h1.................................................................................... 239 9.4.1 operation as interval ti mer/square-wave out put.......................................................................... 239 9.4.2 operation as pw m output mode .................................................................................................24 2 9.4.3 carrier generator mode operati on (8-bit time r h1 onl y)...............................................................248 chapter 10 watch timer ..................................................................................................... ........ 255 10.1 functions of watch timer ..................................................................................................... 25 5 10.2 configuration of watch timer ..... .......................................................................................... 257 10.3 register controlling watch timer ........................................................................................ 257 10.4 watch timer operations ........................................................................................................ 2 59 10.4.1 watch timer operation .......................................................................................................... .......259 10.4.2 interval time r operat ion ....................................................................................................... ........260 10.5 cautions for watch timer...................................................................................................... 2 61 chapter 11 watchdog timer .................................................................................................. ... 262 11.1 functions of watchdog timer....................................... ........................................................ 262 11.2 configuration of watchdog timer ............................... ......................................................... 264 11.3 registers controlling watchdog timer ................................................................................ 265 11.4 operation of watchdog timer ............................................................................................... 267 11.4.1 watchdog timer operation when ?rin g-osc cannot be stopped? is selected by mask option.....267 11.4.2 watchdog timer operation when ?ring-osc can be st opped by software? is selected by mask option ......................................................................................................................... .................268 11.4.3 watchdog timer operation in stop mode (when ? ring-osc can be stopped by software? is selected by mask opt ion) ....................................................................................................... .....269 11.4.4 watchdog timer operation in halt mode (when ?r ing-osc can be stopped by software? is selected by mask opt ion) ....................................................................................................... .....271 chapter 12 clock output/buzzer output controller............................................... 272 12.1 functions of clock ou tput/buzzer output contro ller ........................................................ 272 12.2 configuration of clock output/buz zer output controller .................................................. 273 12.3 register controlling clock output/b uzzer output controller ........................................... 273 12.4 clock output/buzzer output contro ller operations ........................................................... 276 12.4.1 clock output o peratio n ......................................................................................................... .......276 12.4.2 operation as buzzer out put..................................................................................................... ....276 chapter 13 a/d converter ................................................................................................... ...... 277 13.1 functions of a/d con verter................................................................................................... 27 7 13.2 configuration of a/d converter .. .......................................................................................... 278 13.3 registers used in a/d converter .......................................................................................... 280 13.4 a/d converter operations ..................................................................................................... 28 6 13.4.1 basic operations of a/d conv erter.............................................................................................. .286
user?s manual u15947ej2v0ud 16 13.4.2 input voltage and conv ersion re sults .......................................................................................... 2 88 13.4.3 a/d converter operation mode................................................................................................... . 289 13.5 how to read a/d converter charac teristics table ............................................................. 292 13.6 cautions for a/d converter.................................................................................................... 2 94 chapter 14 serial interface uart0 ...................................................................................... 299 14.1 functions of serial interface uart0 ............................... ..................................................... 299 14.2 configuration of serial interfac e uart0 .............................................................................. 300 14.3 registers controlling serial interface uart0 ....... .............................................................. 303 14.4 operation of serial interface uart0............................. ........................................................ 308 14.4.1 operation st op m ode............................................................................................................ ...... 308 14.4.2 asynchronous serial inte rface (uart) mode ............................................................................. 309 14.4.3 dedicated baud rate generator.................................................................................................. . 315 chapter 15 serial interface uart6 ...................................................................................... 320 15.1 functions of serial interface uart6 ............................... ..................................................... 320 15.2 configuration of serial interfac e uart6 .............................................................................. 324 15.3 registers controlling serial interface uart6 ....... .............................................................. 327 15.4 operation of serial interface uart6............................. ........................................................ 335 15.4.1 operation st op m ode............................................................................................................ ...... 335 15.4.2 asynchronous serial inte rface (uart) mode ............................................................................. 336 15.4.3 dedicated baud rate generator.................................................................................................. . 351 chapter 16 serial interfaces csi10 and csi11 ................................................................ 358 16.1 functions of serial interfaces csi10 and csi11 .................................................................. 358 16.2 configuration of serial interfaces csi10 and csi11 . .......................................................... 359 16.3 registers controlling serial interfaces csi10 a nd csi11................................................... 361 16.4 operation of serial interfaces csi 10 and csi11 .................................................................. 367 16.4.1 operation st op m ode............................................................................................................ ...... 367 16.4.2 3-wire serial i/o mode ......................................................................................................... ....... 368 chapter 17 serial interface csia0........................................................................................ 3 78 17.1 functions of serial interface csia0.............................. ........................................................ 378 17.2 configuration of serial interfac e csia0 ............................................................................... 379 17.3 registers controlling serial inte rface csia0....................................................................... 381 17.4 operation of serial interface csia0 .............................. ........................................................ 390 17.4.1 operation st op m ode............................................................................................................ ...... 390 17.4.2 3-wire serial i/o mode ......................................................................................................... ....... 391 17.4.3 3-wire serial i/o mode with auto matic transmit/recei ve func tion ................................................. 396 chapter 18 multiplier/divider ............................................................................................... .... 418 18.1 functions of multiplier/divider ...................................... ........................................................ 41 8 18.2 configuration of multiplier/divide r........................................................................................ 418 18.3 register controlling multiplier/div ider ................................................................................. 423 18.4 operations of multiplier/divider . ........................................................................................... 424
user?s manual u15947ej2v0ud 17 18.4.1 multiplication operation ....................................................................................................... ........424 18.4.2 division op eratio n............................................................................................................. ...........426 chapter 19 interrupt functions ............................................................................................ 4 28 19.1 interrupt function types ....................................................................................................... 428 19.2 interrupt sources and configuration........................ ............................................................ 428 19.3 registers controlling interrupt functi ons ........................................................................... 432 19.4 interrupt servicing operations.... .......................................................................................... 439 19.4.1 maskable interrupt requ est acknowle dgement ............................................................................439 19.4.2 software interrupt requ est acknowle dgment ...............................................................................441 19.4.3 multiple interru pt servicing ................................................................................................... .......442 19.4.4 interrupt r equest hold ......................................................................................................... .........445 chapter 20 key interrupt function ..................................................................................... 446 20.1 functions of key inte rrupt..................................................................................................... 446 20.2 configuration of key interrupt .............................................................................................. 446 20.3 register controlling key interrupt............................... ......................................................... 447 chapter 21 standby function ................................................................................................ .. 448 21.1 standby function and configuration ................................................................................... 448 21.1.1 standby fu ncti on ............................................................................................................... ..........448 21.1.2 registers controlling standby f unction......................................................................................... 450 21.2 standby function operation ......................................... ........................................................ 452 21.2.1 halt mode ...................................................................................................................... ...........452 21.2.2 stop mode ...................................................................................................................... ..........457 chapter 22 reset function .................................................................................................. ..... 461 22.1 register for confirming reset source ................................................................................. 468 chapter 23 clock monitor ................................................................................................... ..... 469 23.1 functions of clock monitor ................................................................................................... 46 9 23.2 configuration of clock monitor.................................... ......................................................... 469 23.3 registers controlling clock monitor ...................... .............................................................. 4 70 23.4 operation of clock monitor ................................................................................................... 47 1 chapter 24 power-on-clear circuit ..................................................................................... 476 24.1 functions of power-on-clear circuit .................................................................................... 476 24.2 configuration of power-on-clear ci rcuit ............................................................................. 477 24.3 operation of power-on-clear circuit ........................ ............................................................ 477 24.4 cautions for power-on-clear circui t .................................................................................... 478 chapter 25 low-voltage detector ....................................................................................... 480 25.1 functions of low-voltage de tector ...................................................................................... 480 25.2 configuration of low-voltage detect or................................................................................ 480 25.3 registers controlling low-voltage de tector....................................................................... 481
user?s manual u15947ej2v0ud 18 25.4 operation of low-voltage detector .............................. ........................................................ 484 25.5 cautions for low-voltage detector............................... ........................................................ 488 chapter 26 regulator ........................................................................................................ ......... 492 26.1 outline of regulator ........................................................................................................... .... 492 chapter 27 mask options .................................................................................................... ....... 494 chapter 28 28.1 internal memory size switching register .................. .......................................................... 496 28.2 internal expansion ram size switching register..... .......................................................... 497 28.3 writing with flash programmer .................................... ........................................................ 498 28.4 programming environment.................................................................................................... 505 28.5 communication mode ............................................................................................................ 5 05 28.6 processing of pins on board................................................................................................. 509 28.6.1 v pp pin........................................................................................................................... ............. 509 28.6.2 serial inte rface pins .......................................................................................................... .......... 510 28.6.3 reset pin...................................................................................................................... ............ 512 28.6.4 port pins ...................................................................................................................... ............... 512 28.6.5 regc pin ....................................................................................................................... ............ 512 28.6.6 other signa l pi ns .............................................................................................................. .......... 512 28.6.7 power su pply................................................................................................................... ........... 512 28.7 programming method............................................................................................................. 513 28.7.1 controlling fl ash me mory....................................................................................................... ..... 513 28.7.2 flash memory pr ogramming mode ............................................................................................. 514 28.7.3 selecting communi cation mode.................................................................................................. 5 14 28.7.4 communication command s ........................................................................................................ 5 15 chapter 29 instruction set................................................................................................. ...... 516 29.1 conventions used in operation list............................. ........................................................ 516 29.1.1 operand identifiers and sp ecification method s........................................................................... 516 29.1.2 description of oper ation co lumn ................................................................................................ . 517 29.1.3 description of fl ag operati on colu mn .................................................................................... ...... 517 29.2 operation list................................................................................................................. ......... 518 29.3 instructions listed by addressing type ...................... ........................................................ 526 chapter 30 electrical specifications (standard products, (a) grade products).............................................. 529 chapter 31 electrical specifications ((a1) grade products) ................................ 554 chapter 32 electrical specifications ((a2) grade products) ................................ 575 chapter 33 package drawings ................................................................................................ 591
user?s manual u15947ej2v0ud 19 chapter 34 recommended soldering conditions........................................................... 593 chapter 35 cautions for wait .............................................................................................. .. 596 35.1 cautions for wait .............................................................................................................. ...... 596 35.2 peripheral hardware that generates wait........................................................................... 597 35.3 example of wait occurrence........................................ ......................................................... 598 appendix a development tools .............................................................................................. 5 99 a.1 software package ............................................................................................................... .... 602 a.2 language processing software ................. ........................................................................... 603 a.3 control software............................................................................................................... ...... 604 a.4 flash memory writing tools ........................................ ......................................................... 604 a.5 debugging tools (hardware) ..................... ........................................................................... 605 a.5.1 when using in-circuit emulators ie-78k0-ns and ie -78k0-ns -a ...............................................605 a.5.2 when using in-circuit em ulator ie- 78k0k1- et ............................................................................606 a.6 debugging tools (software).......................................... ........................................................ 607 a.7 embedded software .............................................................................................................. . 608 appendix b notes on target system design................................................................... 609 appendix c register index .................................................................................................. ....... 614 c.1 register index (in alphabetical order with resp ect to register names)......................... 614 c.2 register index (in alphabetical order with resp ect to register symbol)........................ 618 appendix d revision history ................................................................................................ ..... 622
user?s manual u15947ej2v0ud 20 list of figures (1/10) figure no. title page 2-1 pin i/o cir cuit list ....................................................................................................... ..............................59 3-1 memory map ( 3-2 memory map ( 3-3 memory map ( 3-4 memory map ( 3-5 memory map ( 3-6 correspondence between data memory and addressing ( 3-7 correspondence between data memory and addressing ( 3-8 correspondence between data memory and addressing ( 3-9 correspondence between data memory and addressing ( 3-10 correspondence between data memory and addressing ( 3-11 format of program count er ................................................................................................. .....................74 3-12 format of progr am status word ............................................................................................. ..................74 3-13 format of stack po inter ................................................................................................... .........................75 3-14 data to be sa ved to sta ck memory .......................................................................................... ................76 3-15 data to be rest ored from st ack me mory ..................................................................................... ............77 3-16 configuration of g eneral-purpose registers ................................................................................ ............78 4-1 port types ................................................................................................................. ...............................96 4-2 block diagram of p00, p03, and p05 ......................................................................................... ..............99 4-3 block diagram of p01 an d p06............................................................................................... ................100 4-4 block diagr am of p02 ....................................................................................................... ......................101 4-5 block diagr am of p04 ....................................................................................................... ......................102 4-6 block diagr am of p10 ....................................................................................................... ......................103 4-7 block diagram of p11 an d p14............................................................................................... ................104 4-8 block diagram of p12 an d p15............................................................................................... ................105 4-9 block diagr am of p13 ....................................................................................................... ......................106 4-10 block diagram of p16 an d p17.............................................................................................. .................107 4-11 block diagram of p20 to p27............................................................................................... ...................108 4-12 block diagram of p30 to p32............................................................................................... ...................109 4-13 block diagr am of p33 ...................................................................................................... .......................110 4-14 block diagram of p40 to p47............................................................................................... ...................111 4-15 block diagram of p50 to p57............................................................................................... ...................112 4-16 block diagram of p60 to p63............................................................................................... ...................113 4-17 block diagram of p64, p65, and p67 ........................................................................................ .............114 4-18 block diagr am of p66 ...................................................................................................... .......................115 4-19 block diagram of p70 to p77............................................................................................... ...................116 4-20 block diagr am of p120 ..................................................................................................... ......................117 4-21 block diagr am of p130 ..................................................................................................... ......................118 4-22 block diagram of p140 a nd p 141............................................................................................ ...............119
user?s manual u15947ej2v0ud 21 list of figures (2/10) figure no. title page 4-23 block diagr am of p142 ..................................................................................................... ...................... 120 4-24 block diagr am of p143 ..................................................................................................... ...................... 121 4-25 block diagram of p144 a nd p 145............................................................................................ ............... 122 4-26 format of po rt mode r egister .............................................................................................. .................. 123 4-27 format of port r egister ................................................................................................... ....................... 126 4-28 format of pull-up re sistor opti on regi ster ................................................................................ ............ 127 5-1 memory map when using external bus interface ............................................................................... ... 130 5-2 format of memory expans ion mode regi ster (mem)............................................................................. 132 5-3 pins specified for address (with 5-4 format of memory expansion wait setting r egister (mm)..................................................................... 1 34 5-5 instruction fetch fr om external memory ..................................................................................... ............ 136 5-6 external memo ry read timing ................................................................................................ ............... 137 5-7 external memo ry write timing ............................................................................................... ................ 138 5-8 external memory r ead modify wr ite ti ming ................................................................................... ....... 139 5-9 connection example of 6-1 block diagram of clock g enerat or ........................................................................................... .............. 142 6-2 format of processor clo ck control regi ster (pcc) ........................................................................... .... 144 6-3 format of ring-osc mode register (rcm) ..................................................................................... ...... 145 6-4 format of main clock mode regist er (mcm) ................................................................................... ...... 146 6-5 format of main osc control regi ster (moc) .................................................................................. ...... 147 6-6 format of oscillation stabilization ti me counter status register (ostc) ............................................. 148 6-7 format of oscillation stabilizati on time select r egister (o sts) ........................................................... 1 49 6-8 examples of external circuit of x1 oscilla tor .............................................................................. ........... 150 6-9 examples of external circuit of subsystem clock osc illator ................................................................. . 150 6-10 examples of incorre ct resonator connec tion ................................................................................ ........ 151 6-11 subsystem clo ck feedback re sistor ......................................................................................... ............ 153 6-12 timing diagram of cpu de fault start us ing ring- osc ........................................................................ . 155 6-13 status tr ansition diagram ................................................................................................. ..................... 156 6-14 switching from ri ng-osc clock to x1 input clock (flowc hart).............................................................. 1 63 6-15 switching from x1 input clock to ring-osc clock (flowchart).............................................................. 1 64 6-16 switching from x1 input clock to subsystem clo ck (flowcha rt) ............................................................ 16 5 6-17 switching from subsystem clo ck to x1 input clo ck (flowcha rt) ............................................................ 16 6 7-1 block diagram of 16-bi t timer/event counter 00 ............................................................................. ...... 169 7-2 block diagram of 16-bit timer/event counter 01 ( 7-3 format of 16-bit ti mer counter 0n (tm 0n)................................................................................... .......... 171 7-4 format of 16-bit timer capture/ compare register 00n (c r00n) ........................................................... 171 7-5 format of 16-bit timer capture/ compare register 01n (c r01n) ........................................................... 173 7-6 format of 16-bit timer mode control register 00 (tmc 00) ................................................................... 1 75
user?s manual u15947ej2v0ud 22 list of figures (3/10) figure no. title page 7-7 format of 16-bit timer mode control register 01 (tmc 01) ...................................................................1 76 7-8 format of capture/compare control register 00 (crc 00) .................................................................... 17 7 7-9 format of capture/compare control register 01 (crc 01) .................................................................... 17 8 7-10 format of 16-bit timer out put control regi ster 00 (toc00)................................................................. .179 7-11 format of 16-bit timer out put control regi ster 01 (toc01)................................................................. .180 7-12 format of prescaler mode register 00 (p rm00).............................................................................. ......182 7-13 format of prescaler mode register 01 (p rm01).............................................................................. ......183 7-14 format of port m ode register 0 (pm0) ...................................................................................... .............184 7-15 control register settings for interval ti mer oper ation .................................................................... .......186 7-16 interval timer configurati on diagr am ...................................................................................... ...............187 7-17 timing of interv al timer o peration ........................................................................................ .................187 7-18 control register settings for ppg output operation ........................................................................ ......189 7-19 configurat ion diagram of ppg output....................................................................................... .............190 7-20 ppg output operation timing ............................................................................................... .................190 7-21 cr01n capture operation with rising edge spec ified ........................................................................ ...191 7-22 control register settings for pulse wi dth measurement with free-running counter and one capture register (w hen ti00n and cr01n are us ed) ............................................................ 192 7-23 configuration di agram for pulse width measurem ent with free-runn ing count er ................................193 7-24 timing of pulse width measurement operation with free-running counter and one capture register (wit h both edges specifi ed) ......................................................................... 19 3 7-25 control register settings for measurement of two pulse wi dths with free-ru nning co unter ...............194 7-26 timing of pulse width measurement operation with free-running counter (with both edge s specif ied).................................................................................................... ................195 7-27 control register settings for pulse wi dth measurement with free-running counter and two capture regist ers (with rising ed ge spec ified) ............................................................................. 196 7-28 timing of pulse width measurement operation with free-running counter and two capture registers (wit h rising edge s pecifie d)....................................................................... 19 7 7-29 control register settings for pulse width measurement by means of restart (with rising ed ge specif ied) ................................................................................................... ................198 7-30 timing of pulse widt h measurement operation by means of re start (with rising edge specified) .......198 7-31 control register settings in external ev ent counter mode (with ris ing edge spec ified) .......................200 7-32 configur ation diagram of exte rnal event count er ........................................................................... .......201 7-33 external event counter operation timing (with rising ed ge specif ied) .................................................201 7-34 control register settings in square-wave output mode...................................................................... ..202 7-35 square-wave out put operati on timi ng....................................................................................... ...........203 7-36 control register settings for one-s hot pulse output with software tr igger ..........................................205 7-37 timing of one-shot pulse out put operation with software tr igger ........................................................206 7-38 control register settings for one-s hot pulse output with external trigger (with rising ed ge specif ied) ................................................................................................... ................207 7-39 timing of one-shot pulse ou tput operation with external tri gger (with rising ed ge specif ied) ...........208 7-40 start timing of 16-bit timer counter 0n (tm0n)............................................................................ .........209
user?s manual u15947ej2v0ud 23 list of figures (4/10) figure no. title page 7-41 operation timi ng of ovf 0n fl ag............................................................................................ ................ 210 7-42 capture register data retent ion ti ming .................................................................................... ............ 210 8-1 block diagram of 8-bi t timer/event counte r 50 .............................................................................. ....... 212 8-2 block diagram of 8-bi t timer/event counte r 51 .............................................................................. ....... 213 8-3 format of 8-bit ti mer counter 5n (tm 5n).................................................................................... ........... 214 8-4 format of 8-bit timer co mpare register 5n ( cr5n) ........................................................................... ... 215 8-5 format of timer clock sele ction register 50 (t cl50) ........................................................................ ... 216 8-6 format of timer clock sele ction register 51 (t cl51) ........................................................................ ... 217 8-7 format of 8-bit timer mode control regist er 50 (t mc50) ..................................................................... 218 8-8 format of 8-bit timer mode control regist er 51 (t mc51) ..................................................................... 219 8-9 format of port m ode register 1 (pm1)....................................................................................... ............ 220 8-10 format of port m ode register 3 (pm3)...................................................................................... ............. 220 8-11 interval time r operatio n timi ng ........................................................................................... .................. 221 8-12 external event counter operation timing (with rising ed ge specif ied) ................................................ 223 8-13 square-wave out put operati on timi ng ....................................................................................... .......... 225 8-14 pwm output operation timing............................................................................................... ................ 227 8-15 timing of operat ion with cr5n changed ..................................................................................... .......... 228 8-16 8-bit timer count er 5n star t timing ....................................................................................... ................ 229 9-1 block diagram of 8-bit ti mer h0 ............................................................................................ ................ 231 9-2 block diagram of 8-bit ti mer h1 ............................................................................................ ................ 232 9-3 format of 8-bit timer h co mpare register 0n (c mp0n) ........................................................................ 233 9-4 format of 8-bit timer h co mpare register 1n (c mp1n) ........................................................................ 233 9-5 format of 8-bit timer h mode register 0 (tmh md0) ........................................................................... . 235 9-6 format of 8-bit timer h mode register 1 (tmh md1) ........................................................................... . 237 9-7 format of 8-bit timer h carrier control register 1 (tmc yc1) .............................................................. 23 8 9-8 format of port m ode register 1 (pm1)....................................................................................... ............ 238 9-9 register setting during interval timer/ square-wave output operat ion ................................................ 239 9-10 timing of interval timer/ square-wave outp ut oper ation..................................................................... .. 240 9-11 register setting in pwm out put m ode....................................................................................... ............ 242 9-12 operation timing in pwm out put m ode ....................................................................................... .......... 244 9-13 transfe r timing ........................................................................................................... ........................... 249 9-14 register setting in carrier gener ator mode ................................................................................ ........... 250 9-15 carrier generator mode operati on timing ................................................................................... .......... 252 10-1 watch timer block dia gram ................................................................................................. .................. 255 10-2 format of watch timer oper ation mode regist er (wtm) ...................................................................... 2 58 10-3 operation timing of watc h timer/interv al timer ............................................................................ ........ 260 10-4 example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) .... 261
user?s manual u15947ej2v0ud 24 list of figures (5/10) figure no. title page 11-1 block diagram of watchdog timer ........................................................................................... ..............264 11-2 format of watchdog time r mode regist er (wdtm)............................................................................. ..265 11-3 format of watchdog time r enable regist er (wdte) ........................................................................... ..266 11-4 operation in stop mode (cpu clock a nd wdt operation clock: x1 inpu t clock) ...............................269 11-5 operation in stop mode (cpu clock: x1 i nput clock, wdt operation clock: ring-osc clock)........269 11-6 operation in stop mode (cpu clock: ring-os c clock, wdt operation clo ck: x1 input clock).........270 11-7 operation in stop mode (cpu clock a nd wdt operation clock: ring-osc clock) ............................271 11-8 operation in halt mode .................................................................................................... ....................271 12-1 block diagram of clock outp ut/buzzer output contro ller.................................................................... ...272 12-2 format of clock output selection regi ster (cks) ........................................................................... .......274 12-3 format of port m ode register 14 (pm 14) .................................................................................... ...........275 12-4 remote control output applicati on exam ple................................................................................. .........276 13-1 block diagram of a/d conv erter............................................................................................ .................277 13-2 format of a/d converte r mode regist er (adm) ............................................................................... ......281 13-3 timing chart when boost referenc e voltage generat or is used ..........................................................282 13-4 format of analog input channel specification r egister (ads)............................................................... 283 13-5 format of a/d conversion result regi ster (adcr) ........................................................................... ....284 13-6 format of power-fail com parison mode regi ster (pfm) ....................................................................... 285 13-7 format of power-fail comparis on threshold regi ster (pft).................................................................2 85 13-8 basic operation of a/d c onverter.......................................................................................... .................287 13-9 relationship between analog input voltage and a/d co nversion re sult ...............................................288 13-10 a/d conversi on operation ................................................................................................. .....................289 13-11 power-fail detection (whe n pfen = 1 and pfcm = 0) ........................................................................ .290 13-12 overa ll erro r ............................................................................................................ ...............................292 13-13 quantizat ion e rror....................................................................................................... ............................292 13-14 zero-scale error ............................................................................................................... 293 13-15 full-scal e error......................................................................................................... ..............................293 13-16 integral linearity error ........................................................................................................ 293 13-17 differential li nearity error ............................................................................................. ..........................293 13-18 circuit configuration of series resi stor string.......................................................................... ..............294 13-19 analog input pin con nection .............................................................................................. ....................295 13-20 timing of a/d conversion en d interrupt req uest gener ation ................................................................ 296 13-21 timing of a/d converter sampling and a/d conversion start de lay ......................................................297 13-22 internal equivalent circuit of anin pin .................................................................................. ..................298 14-1 block diagram of se rial interf ace uart0................................................................................... ............301 14-2 format of asynchronous serial interface operation mode register 0 (asim0 )......................................303 14-3 format of asynchronous seri al interface reception error st atus register 0 (asis0)............................305 14-4 format of baud rate generator control register 0 (brg c0) ................................................................30 6
user?s manual u15947ej2v0ud 25 list of figures (6/10) figure no. title page 14-5 format of port m ode register 1 (pm1)...................................................................................... ............. 307 14-6 format of normal uart transmit/rec eive data............................................................................... ..... 310 14-7 example of normal uart trans mit/receive data waveform................................................................ 310 14-8 transmission completion interrupt re quest ti ming.......................................................................... ..... 312 14-9 reception completion interrupt req uest ti ming ............................................................................. ....... 313 14-10 noise filt er circuit ..................................................................................................... ............................. 314 14-11 configuration of baud rate generat or ..................................................................................... .............. 315 14-12 permissible baud rate range during reception ............................................................................. ...... 318 15-1 lin transmissi on operat ion ................................................................................................ ................... 321 15-2 lin recepti on operat ion ................................................................................................... ..................... 322 15-3 port configuration for lin reception operation ............................................................................ ......... 323 15-4 block diagram of se rial interf ace uart6 ................................................................................... ........... 325 15-5 format of asynchronous serial interface operation mode register 6 (asim6 )...................................... 327 15-6 format of asynchronous seri al interface reception error st atus register 6 (asis6)............................ 329 15-7 format of asynchronous se rial interface transmission st atus register 6 (asif6)................................ 330 15-8 format of clock select ion register 6 (c ksr6) .............................................................................. ........ 331 15-9 format of baud rate generator control register 6 (brg c6)................................................................ 33 2 15-10 format of asynchronous serial interface contro l register 6 (asic l6) .................................................. 333 15-11 format of input switch control regist er (isc)............................................................................ ............ 334 15-12 format of port m ode register 1 (pm1)..................................................................................... .............. 334 15-13 format of normal uart transmit/rec eive data.............................................................................. ...... 338 15-14 example of normal uart trans mit/receive data waveform................................................................ 339 15-15 normal transmission completi on interrupt r equest timing .................................................................. 341 15-16 example of continuous transmission proc essing flow ....................................................................... .. 343 15-17 timing of starting co ntinuous tr ansmission ............................................................................... ........... 344 15-18 timing of ending co ntinuous tr ansmission ................................................................................. .......... 345 15-19 reception completion interrupt req uest ti ming ............................................................................ ........ 346 15-20 reception e rror inte rrupt ................................................................................................ ........................ 347 15-21 noise filt er circuit ..................................................................................................... ............................. 348 15-22 example of setting procedure of sbf transmission (flowchart) ........................................................... 34 9 15-23 sbf tr ansmissi on ......................................................................................................... ......................... 349 15-24 sbf re ception ............................................................................................................ ........................... 350 15-25 configuration of baud rate generat or ..................................................................................... .............. 352 15-26 permissible baud rate range during reception ............................................................................. ...... 355 15-27 data frame length duri ng continuous transmi ssion......................................................................... ... 357 16-1 block diagram of se rial interf ace csi10 ................................................................................... ............. 359 16-2 block diagram of serial interface csi11 ( 16-3 format of serial operati on mode register 10 (csi m10) ...................................................................... .. 361 16-4 format of serial operati on mode register 11 (csi m11) ...................................................................... .. 362
user?s manual u15947ej2v0ud 26 list of figures (7/10) figure no. title page 16-5 format of serial clock sele ction register 10 (csic10)..................................................................... .....363 16-6 format of serial clock sele ction register 11 (csic11)..................................................................... .....365 16-7 format of port m ode register 0 (pm0) ...................................................................................... .............366 16-8 format of port m ode register 1 (pm1) ...................................................................................... .............366 16-9 timing in 3-wire serial i/o mode .......................................................................................... ..................372 16-10 timing of clo ck/data phase ............................................................................................... ....................374 16-11 output operati on of firs t bit ............................................................................................ .......................375 16-12 output value of so1n pin (l ast bit) ...................................................................................... .................376 17-1 block diagram of se rial interf ace csia0 ................................................................................... .............380 17-2 format of automatic da ta transfer address count register 0 (adtc0 )................................................381 17-3 format of serial operation mode sp ecification regist er 0 (csi ma0) ....................................................382 17-4 format of serial stat us register 0 (csi s0) ................................................................................ ............383 17-5 format of serial tri gger register 0 (csi t0) ............................................................................... ............385 17-6 format of divisor select ion register 0 (brg ca0) ........................................................................... ......386 17-7 format of automatic data transfer address point specif ication register 0 (adt p0) ............................386 17-8 format of automati c data transfer interval specif ication register 0 (adt i0) ........................................388 17-9 format of port m ode register 14 (pm 14) .................................................................................... ...........389 17-10 3-wire serial i/o mode timing............................................................................................ ....................393 17-11 format of trans mit/receive data .......................................................................................... .................394 17-12 transfer bit order switchi ng circu it..................................................................................... ...................395 17-13 automatic transmission/recept ion mode operatio n timing s ................................................................39 9 17-14 automatic transmission/ reception mode flowchart .......................................................................... ....400 17-15 internal buffer ram operation in 6-byte transmission/reception (in automatic transmi ssion/recept ion mode) ..................................................................................... ...401 17-16 automatic transmission mode operat ion ti ming ............................................................................. ......403 17-17 automatic transmi ssion mode fl owchart .................................................................................... ...........404 17-18 internal buffer ram operation in 6-byte transmission (in automa tic transmissi on mode) ...................405 17-19 repeat transmission mode operatio n timi ng................................................................................ ........407 17-20 repeat transmissi on mode flow chart....................................................................................... .............408 17-21 internal buffer ram operation in 6-byte transmission (in repe at transmissi on mode) .......................409 17-22 format of csia0 tr ansmit/recei ve data.................................................................................... ............411 17-23 automatic transmission/recept ion suspension an d restar t .................................................................4 12 17-24 system configur ation when busy contro l option is used .................................................................... .413 17-25 operation timing when busy control option is used (when busylv0 = 1) ........................................414 17-26 busy signal and wait release (when bu sylv0 = 1).......................................................................... ..414 17-27 operation timing when busy & strobe control options are used (when busyl v0 = 1).....................415 17-28 operation timing of bit shift detection function by busy signal (when busylv0 = 0)........................416 17-29 automatic transmit/r eceive inte rval time ................................................................................. ............417
user?s manual u15947ej2v0ud 27 list of figures (8/10) figure no. title page 18-1 block diagram of multiplier /divider....................................................................................... .................. 419 18-2 format of remainder da ta register 0 (sdr0) ................................................................................ ....... 420 18-3 format of multiplicati on/division data register a0 (md a0h, md a0l) ................................................... 421 18-4 format of multiplic ation/divisi on data register b0 (mdb0)................................................................. ... 422 18-5 format of multiplier/divider control register 0 (dm uc0) ................................................................... .... 423 18-6 timing chart of multip lication operation (00dah 18-7 timing chart of division operation (dcba2586h 19-1 basic configuration of interrupt func tion ................................................................................. .............. 431 19-2 format of interrupt request flag re gisters (if0l, if0h , if1l, if1h) .................................................... 434 19-3 format of interrupt mask flag r egisters (mk0l, mk0h , mk1l, mk 1h) ................................................ 435 19-4 format of priority specification flag registers (pr0l, pr 0h, pr1l, pr1h) ......................................... 436 19-5 format of external interrupt rising edge enable register (egp) and external interrupt falling e dge enable regist er (egn )................................................................... 437 19-6 format of progr am status word............................................................................................. ................ 438 19-7 interrupt request acknowle dgment proces sing algor ithm ..................................................................... 440 19-8 interrupt request acknowledg ment timing (min imum ti me) ................................................................. 441 19-9 interrupt request acknowledg ment timing (max imum ti me) ................................................................ 441 19-10 examples of multiple interrupt servic ing ................................................................................. ............... 443 19-11 interrupt request hold ................................................................................................... ........................ 445 20-1 block diagram of key in terrupt............................................................................................ ................... 446 20-2 format of key return mode regist er (krm).................................................................................. ........ 447 21-1 format of oscillation stabilization ti me counter status register (ostc) ............................................. 450 21-2 format of oscillation stabilizati on time select r egister (osts) ........................................................... 451 21-3 halt mode release by in terrupt reques t generat ion ......................................................................... . 454 21-4 halt mode releas e by rese t input.......................................................................................... .......... 455 21-5 operation timing when stop mode is released ............................................................................... .. 458 21-6 stop mode release by in terrupt reques t generat ion......................................................................... . 459 21-7 stop mode releas e by rese t input .......................................................................................... ......... 460 22-1 block diagram of reset f unction ........................................................................................... ................ 462 22-2 timing of rese t by reset input............................................................................................ ................ 463 22-3 timing of reset due to watchdog time r overflow............................................................................ ..... 463 22-4 timing of reset in st op mode by reset input ............................................................................... .... 464 22-5 format of reset contro l flag regist er (resf) .............................................................................. ........ 468 23-1 block diagram of clock m onitor ............................................................................................ ................. 469 23-2 format of clock monitor mode regist er (clm) ............................................................................... ....... 470 23-3 timing of clo ck monitor ................................................................................................... ....................... 472
user?s manual u15947ej2v0ud 28 list of figures (9/10) figure no. title page 24-1 block diagram of power-on-clear circuit ................................................................................... ............477 24-2 timing of internal reset signal generation in power- on-clear cir cuit ...................................................477 24-3 example of software proce ssing after releas e of re set ..................................................................... ..478 25-1 block diagram of low-voltage detect or ..................................................................................... ............480 25-2 format of low-voltage de tection regist er (lvim) ........................................................................... ......482 25-3 format of low-voltage detection level selection re gister (l vis).........................................................48 3 25-4 timing of low-voltage detector internal reset si gnal genera tion .........................................................48 5 25-5 timing of low-voltage detector interrupt sig nal gene ration................................................................ ..487 25-6 example of software proce ssing after releas e of re set ..................................................................... ..489 26-1 block diagram of regulator pe riphery...................................................................................... ..............492 26-2 regc pin connection ....................................................................................................... .....................493 28-1 format of internal memory si ze switching r egister (ims) ................................................................... ..496 28-2 format of internal expansion ra m size switching register (ixs) .........................................................497 28-3 example of wiring adapter for flash memory writing in 3-wire seri al i/o (csi10) mode ......................500 28-4 example of wiring adapter for flash memory wr iting in 3-wire serial i/o (csi10 + hs) m ode .............501 28-5 example of wiring adapter for flash me mory writing in ua rt (uart0 ) mode .....................................502 28-6 example of wiring adapter for flash memo ry writing in uart (uart0 + hs ) mode ............................503 28-7 example of wiring adapter for flash me mory writing in ua rt (uart6 ) mode .....................................504 28-8 environment for writing program to fl ash me mory ........................................................................... .....505 28-9 communication with dedicat ed flash programme r (csi10 )...................................................................50 5 28-10 communication with dedicated flash programmer (csi10 + hs)..........................................................506 28-11 communication with dedicat ed flash programme r (uart0 ).................................................................506 28-12 communication with dedicated fl ash programmer (u art0 + hs)........................................................507 28-13 communication with dedicat ed flash programme r (uart6 ).................................................................507 28-14 example of connection of v pp pin ..........................................................................................................509 28-15 signal collision (input pi n of serial interface)......................................................................... ................510 28-16 malfunction of other device.............................................................................................. ......................511 28-17 signal collis ion (reset pin)............................................................................................. .....................512 28-18 flash memory mani pulation pr ocedure ...................................................................................... ............513 28-19 flash memory programmi ng m ode............................................................................................ .............514 28-20 communicati on commands................................................................................................... .................515 a-1 development tool configuration ............................................................................................. ...............600 b-1 distance between ie syst em and conversi on a dapter .......................................................................... 609 b-2 connection conditions of target system (when usi ng np-80gc- tq) ..................................................610 b-3 connection conditions of target system (when usi ng np-h80gc- tq)................................................611 b-4 connection conditions of tar get system (when us ing np- 80gk) ........................................................612
user?s manual u15947ej2v0ud 29 list of figures (10/10) figure no. title page b-5 connection conditions of target system (when usi ng np-h80gk- tq) ............................................... 613
user?s manual u15947ej2v0ud 30 list of tables (1/3) table no. title page 1-1 flash memory versions corresponding to mask options of mask rom ve rsions ...................................37 2-1 pin i/o buffer power su pplies .............................................................................................. ....................47 2-2 pin i/o cir cuit types ...................................................................................................... ...........................57 3-1 set values of internal memory size switching register (ims) and internal expansion ram size switching regi ster (i xs).....................................................................61 3-2 internal rom capac ity...................................................................................................... ........................67 3-3 vector table ............................................................................................................... ..............................67 3-4 internal expans ion ram c apacity ............................................................................................ ................68 3-5 special functi on register list ............................................................................................. .....................80 4-1 pin i/o buffer power su pplies .............................................................................................. ....................96 4-2 port functi ons............................................................................................................. ..............................97 4-3 port conf igurat ion ......................................................................................................... ............................98 4-4 pull-up resist or of port 6 ................................................................................................. .......................113 4-5 settings of port mode register and out put latch when using al ternate f unction ................................124 5-1 pin functions in exter nal memory ex pansion mode............................................................................ ...129 5-2 state of ports 4 to 6 pins in external memory expansion mode .............................................................12 9 6-1 configuration of clock g enerator ........................................................................................... ................141 6-2 relationship between cp u clock and minimum instru ction execut ion ti me .........................................145 6-3 relationship between operation clocks in each operation status ........................................................160 6-4 oscillation control flags and clock oscill ation st atus ..................................................................... ......160 6-5 maximum time required to switch between ring-os c clock and x1 i nput clo ck ...............................161 6-6 maximum time required for cpu clock switchover............................................................................. .162 6-7 clock and regi ster se tting ................................................................................................. ....................167 7-1 configuration of 16-bit ti mer/event coun ters 00 and 01..................................................................... ...169 7-2 cr00n capture trigger and valid edges of ti00n and ti01n pins ........................................................172 7-3 cr01n capture trigger and valid edge of ti00n pi n (crc0n2 = 1) ......................................................173 8-1 configuration of 8-bit ti mer/event counte rs 50 an d 51 ...................................................................... ....214 9-1 configuration of 8- bit timers h0 an d h1 .................................................................................... ............230 10-1 watch timer interrupt time ................................................................................................ ....................256 10-2 interval time r interval time .............................................................................................. ......................256 10-3 watch timer configur ation ................................................................................................. ....................257 10-4 watch timer interrupt time ................................................................................................ ....................259
user?s manual u15947ej2v0ud 31 list of tables (2/3) table no. title page 10-5 interval time r interval time .............................................................................................. ...................... 260 11-1 loop detection time of watc hdog time r ..................................................................................... .......... 262 11-2 mask option setting and watc hdog timer oper ation mo de .................................................................. 263 11-3 configuration of watchdog timer ........................................................................................... ................ 264 12-1 clock output/buzzer output controller co nfiguration ....................................................................... ..... 273 13-1 registers of a/d c onverter used on softw are ............................................................................... ........ 278 13-2 settings of adcs and adce................................................................................................. ................. 282 13-3 a/d converter sampling time and a/d conver sion start delay time (adm set value) ........................ 297 13-4 resistance and capa citance values of e quivalent circuit (ref erence va lues)...................................... 298 14-1 configuration of se rial interf ace uart0 ................................................................................... ............. 300 14-2 relationship between re gister settings and pins........................................................................... ....... 309 14-3 cause of re ception error .................................................................................................. ..................... 314 14-4 set data of ba ud rate ge nerator........................................................................................... ................ 317 14-5 maximum/minimum permi ssible baud ra te error ............................................................................... ... 319 15-1 configuration of se rial interf ace uart6 ................................................................................... ............. 324 15-2 relationship between re gister settings and pins........................................................................... ....... 337 15-3 cause of re ception error .................................................................................................. ..................... 347 15-4 set data of ba ud rate ge nerator........................................................................................... ................ 354 15-5 maximum/minimum permi ssible baud ra te error ............................................................................... ... 356 16-1 configuration of serial interfaces csi 10 and cs i11........................................................................ ....... 359 16-2 relationship between re gister settings and pins........................................................................... ....... 369 16-3 so1n out put st atus ........................................................................................................ ....................... 377 17-1 configuration of se rial interf ace csia0................................................................................... ............... 379 17-2 relationship between buffer ram addr ess values and adtp 0 setting va lues .................................... 387 17-3 relationship between re gister settings and pins........................................................................... ....... 392 17-4 relationship between re gister settings and pins........................................................................... ....... 397 18-1 configuration of multiplie r/divider....................................................................................... .................... 418 18-2 functions of mda0 du ring operation execution .............................................................................. ...... 422 19-1 interrupt source list ..................................................................................................... .......................... 429 19-2 flags corresponding to in terrupt reques t sources.......................................................................... ...... 433 19-3 ports corresponding to egpn and eg nn ...................................................................................... ........ 437 19-4 time from generation of maskable interrupt request un til servic ing .................................................... 439
user?s manual u15947ej2v0ud 32 list of tables (3/3) table no. title page 19-5 relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servic ing ..................................................................................................... ..................442 20-1 assignment of key in terrupt dete ction pins................................................................................ ............446 20-2 configuration of key in terrupt ............................................................................................ .....................446 21-1 relationship between operation clocks in each operation status ........................................................448 21-2 operating status es in ha lt mode ........................................................................................... ..............452 21-3 operation in response to interrupt request in halt mode................................................................... 456 21-4 operating status es in st op mode........................................................................................... ..............457 21-5 operation in response to in terrupt request in stop mode ..................................................................4 60 22-1 hardware statuses a fter reset ack nowledg ment .............................................................................. ....465 22-2 resf status when rese t request is gener ated ............................................................................... ...468 23-1 configuration of clock m onitor............................................................................................ ....................469 23-2 operation status of clo ck monitor (when clme = 1) ......................................................................... ...471 27-1 flash memory versions supporting mask options of ma sk rom vers ions ...........................................494 28-1 differences between 28-2 internal memory size switching regi ster se ttings .......................................................................... .......496 28-3 internal expansion ram size switching regi ster se ttings................................................................... ..497 28-4 wiring between 28-5 pin co nnecti on ............................................................................................................ ...........................508 28-6 pins used by each serial in terface ........................................................................................ ................510 28-7 communica tion modes ....................................................................................................... ....................514 28-8 flash memory control commands ............................................................................................. ............515 28-9 response comm ands ......................................................................................................... ...................515 29-1 operand identifiers and specificati on methods ............................................................................. .........516 34-1 surface mounting type soldering co nditi ons................................................................................ .........593 35-1 registers that generate wait and number of cp u wait clocks ...........................................................597 35-2 number of wait clocks and number of execution clocks on occurrence of wait (a/d converter)........598 b-1 distance between ie syst em and conversi on a dapter .......................................................................... 609
user?s manual u15947ej2v0ud 33 chapter 1 outline 1.1 features { minimum instruction execution time can be changed from high speed (0.2 { general-purpose register: 8 bits 32 r egisters (8 bits 8 registers 4 banks) { rom, ram capacities data memory item part number program memory (rom) internal high-speed ram internal expansion ram ? mask rom 60 kb 1024 bytes { buffer ram: 32 bytes (can be used for transfer in 3-wire serial i/o m ode with automatic transmit/receive function) { external memory expansion space: 64 kb (with external bus interface function) { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { short startup is possible via the cpu default start using the on-chip ring-osc { on-chip clock monitor function using on-chip ring-osc { on-chip watchdog timer (operable with ring-osc clock) { on-chip multiplier/divider { on-chip key interrupt function { on-chip clock output/buzzer output controller { on-chip regulator { i/o ports: 67 (n-ch open drain: 4) { timer { serial interface { 10-bit resolution a/d converter: 8 channels note select either of the functions of these alternate-function pins.
chapter 1 outline user?s manual u15947ej2v0ud 34 { supply voltage: v dd = 2.7 to 5.5 v (standard product, (a) grade product) v dd = 3.3 to 5.5 v ((a1) grade product, (a2) grade product) { operating ambient temperature: t a = ? ? ? ? { automotive equipment ? ? { home audio, car audio { av equipment { pc peripheral equipment (keyboards, etc.) { household electrical appliances ? ? { industrial equipment ? ? ?
chapter 1 outline user?s manual u15947ej2v0ud 35 1.3 ordering information (1) mask rom versions part number package quality grade
chapter 1 outline user?s manual u15947ej2v0ud 36 (2) flash memory versions part number package quality grade
chapter 1 outline user?s manual u15947ej2v0ud 37 mask rom versions (
chapter 1 outline user?s manual u15947ej2v0ud 38 1.4 pin configuration (top view) ? 80-pin plastic tqfp (fine pitch) (12 12) ? 80-pin plastic qfp (14 14) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 av ref av ss p120/intp0 p33/ti51/to51/intp4 p32/intp3 p31/intp2 p30/intp1 ic (v pp ) v dd regc v ss x1 x2 reset xt1 xt2 p130 p10/sck10/txd0 p11/si10/rxd0 p12/so10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 p64/rd p65/wr p66/wait p67/astb p00/ti000 p01/ti010/to00 p02/so11 note p03/si11 note p20/ani0 p21/ani1 p22/ani2 p23/ani3 p24/ani4 p25/ani5 p26/ani6 p27/ani7 p70/kr0 p71/kr1 p72/kr2 p73/kr3 p74/kr4 p75/kr5 p76/kr6 p77/kr7 p40/ad0 p41/ad1 p42/ad2 p43/ad3 80 79 78 77 76 75 74 73 72 71 70 69 68 64 63 62 61 67 66 65 21 22 23 24 25 26 27 28 29 30 31 32 33 37 38 39 40 34 35 36 p13/txd6 p14/rxd6 p15/toh0 p16/toh1/intp5 p17/ti50/to50 p140/pcl/intp6 p141/buz/busy0/intp7 p63 p62 ev ss ev dd p61 p60 p142/scka0 p143/sia0 p144/soa0 p145/stb0 p06/ti011 note /to01 note p05/ssi11 note /ti001 note p04/sck11 note note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the pd780146, 780148, and 78f0148. cautions 1. connect the ic (inter nally connected) pin directly to v ss . 2. connect the av ss pin to v ss . 3. connect the regc pin as follows. standard product and (a) grade product (a1) grade product and (a2) grade product when regulator is used connect to v ss via a capacitor (1 f: recommended) ? (regulator cannot be used.) when regulator is not used connect directly to v dd 4. connect the v pp pin to ev ss or v ss during normal operation. remark figures in parentheses apply only to the pd78f0148.
chapter 1 outline user?s manual u15947ej2v0ud 39 pin identification a8 to a15: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input astb: address strobe av ref : analog reference voltage av ss : analog ground busy0: serial busy input buz: buzzer output ev dd : power supply for port ev ss : ground for port ic: internally connected intp0 to intp7: external interrupt input kr0 to kr7: key return p00 to p06: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p33: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p120: port 12 p130: port 13 p140 to p145: port 14 pcl: programmable clock output regc: regulator capacitance reset: reset rxd0, rxd6: receive data rd: read strobe sck10, sck11 note , scka0: serial clock input/output si10, si11 note , sia0: serial data input so10, so11 note , soa1: serial data output ssi11 note : serial interface chip select input stb0: serial strobe ti000, ti010, ti001 note , ti011 note , ti50, ti51: timer input to00, to01 note , to50, to51, toh0, toh1: timer output txd0, txd6: transmit data v dd : power supply v pp : programming power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal oscillator (x1 input clock) xt1, xt2: crystal oscillator (subsystem clock) note so11, si11, sck11, ssi11, ti001, ti011, and to01 are available only in the
chapter 1 outline user?s manual u15947ej2v0ud 40 1.5 k1 family lineup 1.5.1 78k0/kx1 product lineup pd78f0103 flash memory: 24 kb, ram: 768 bytes mask rom: 24 kb, ram: 768 bytes mask rom: 16 kb, ram: 768 bytes mask rom: 8 kb, ram: 512 bytes pd780103 pd780102 pd780101 78k0/kb1: 30-pin (7.62 mm 0.65 mm pitch) pd78f0114 flash memory: 32 kb, ram: 1 kb mask rom: 32 kb, ram: 1 kb mask rom: 24 kb, ram: 1 kb mask rom: 16 kb, ram: 512 bytes pd780114 pd780113 pd780112 mask rom: 8 kb, ram: 512 bytes pd780111 78k0/kc1: 44-pin (10
chapter 1 outline user?s manual u15947ej2v0ud 41 the list of functions in the 78k0/kx1 is shown below. part number item 78k0/kb1 78k0/kc1 78k0/kd1 78k0/ke1 78k0/kf1 package 30 pins 44 pins 52 pins 64 pins 80 pins 16 k 8 k 24 k 8 k 24 k 8 k 24 k 48 k 24 k 48 k mask rom 8 k 24 k ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 1 outline user?s manual u15947ej2v0ud 42 1.5.2 v850es/kx1 product lineup 144-pin plastic lqfp (fine pitch) (20
chapter 1 outline user?s manual u15947ej2v0ud 43 the list of functions in the v850es/kx1 is shown below. timer serial interface function part no. 8-bit 16-bit tmh watch wdt csi csia uart i 2 c a/d d/a rto i/o other
chapter 1 outline user?s manual u15947ej2v0ud 44 1.6 block diagram 16-bit timer/ event counter 00 to00/ti010/p01 ti000/p00 port 0 p00 to p06 7 port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p33 4 port 4 port 5 78k/0 cpu core internal high-speed ram internal expansion ram note rom (flash memory) v ss , ev ss ic (v pp ) v dd , ev dd serial interface csi10 si10/p11 so10/p12 sck10/p10 ani0/p20 to ani7/p27 interrupt control 8-bit timer h0 toh0/p15 8-bit timer h1 toh1/p16 ti50/to50/p17 8-bit timer/ event counter 50 8 a/d converter rxd0/p11 txd0/p10 serial interface uart0 watchdog timer rxd6/p14 txd6/p13 serial interface uart6 av ref av ss intp1/p30 to intp4/p33 4 intp0/p120 8 system control reset x1 x2 clock monitor power on clear/ low voltage indicator poc/lvi control reset control external access port 6 p60 to p67 8 port 7 p70 to p77 port 12 p120 port 13 p130 8 p40 to p47 8 p50 to p57 8 port 14 p140 to p145 6 ring-osc ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 xt1 xt2 16-bit timer/ note event counter 01 to01 note /ti011 note /p06 ti001 note /p05 ti51/to51/p33 8-bit timer/ event counter 51 watch timer serial interface csi11 note si11 note /p03 so11 note /p02 sck11 note /p04 ssi11 note /p05 serial interface csia0 sia0/p143 soa0/p144 scka0/p142 stb0/p145 busy0/p141 intp5/p16 intp6/p140, intp7/p141 2 buzzer output buz/p141 clock output control pcl/p140 key return 8 8 8 kr0/p70 to kr7/p77 multiplier & divider voltage regulator regc note
chapter 1 outline user?s manual u15947ej2v0ud 45 1.7 outline of functions (1/2) note the internal flash memory capacity and internal expa nsion ram capacity can be changed using the internal memory size switching register (ims) and the inte rnal expansion ram size switching register (ixs). item ?
chapter 1 outline user?s manual u15947ej2v0ud 46 (2/2) note select either of the functions of these alternate-function pins. an outline of the timer is shown below. 16-bit timer/ event counters 00 and 01 note 1 8-bit timer/ event counters 50 and 51 8-bit timers h0 and h1 tm00 tm01 note 1 tm50 tm51 tmh0 tmh1 watch timer watchdog timer interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel note 2 1 channel 1 channel operation mode external event counter 1 chann el 1 channel 1 channel 1 channel ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
user?s manual u15947ej2v0ud 47 chapter 2 pin functions 2.1 pin function list there are three types of pi n i/o buffer power supplies: av ref , ev dd , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 v dd pins other than port pins (1) port pins (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note p03 si11 note p04 sck11 note p05 ssi11 note /ti001 note p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011 note /to01 note p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p27 input port 2. 8-bit input-only port. input ani0 to ani7 p30 to p32 intp1 to intp3 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 p40 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ad0 to ad7 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the
chapter 2 pin functions user?s manual u15947ej2v0ud 48 (1) port pins (2/2) pin name i/o function after reset alternate function p50 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input a8 to a15 p60 to p63 n-ch open-drain i/o port. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. ? ?
chapter 2 pin functions user?s manual u15947ej2v0ud 49 (2) non-port pins (1/2) pin name i/o function after reset alternate function intp0 p120 intp1 to intp3 p30 to p32 intp4 p33/ti51/to51 intp5 p16/toh1 intp6 p140/pcl intp7 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p141/buz/busy0 si10 p11/rxd0 si11 note p03 sia0 input serial data input to serial interface input p143 so10 p12 so11 note p02 soa0 output serial data output from serial interface input p144 sck10 p10/txd0 sck11 note p04 scka0 i/o clock input/output for serial interface input p142 ssi11 note input serial interface chip select input input p05/ti001 busy0 input serial interface busy input input p141/buz/intp7 stb0 output serial interface strobe output input p145 rxd0 p11/si10 rxd6 input serial data input to asynch ronous serial interface input p14 txd0 p10/sck10 txd6 output serial data output from asyn chronous serial interface input p13 ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p00 ti001 note external count clock input to 16-bit timer/event counter 01 capture trigger input to captur e registers (cr001, cr011) of 16-bit timer/event counter 01 p05/ssi11 note ti010 capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 p01/to00 ti011 note input capture trigger input to capture register (cr001) of 16-bit timer/event counter 01 input p06/to01 note to00 16-bit timer/event counter 00 output p01/ti010 to01 note output 16-bit timer/event counter 01 output input p06/ti011 note ti50 external count clock input to 8-bit timer/event counter 50 p17/to50 ti51 input external count clock input to 8-bit timer/event counter 51 input p33/to51/intp4 to50 8-bit timer/event counter 50 output p17/ti50 to51 8-bit timer/event counter 51 output p33/ti51/intp4 toh0 8-bit timer h0 output p15 toh1 output 8-bit timer h1 output input p16/intp5 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the
chapter 2 pin functions user?s manual u15947ej2v0ud 50 (2) non-port pins (2/2) pin name i/o function after reset alternate function pcl output clock output (for trimming of x1 i nput clock, subsystem clock) input p140/intp6 buz output buzzer output input p 141/intp7/busy0 ad0 to ad7 i/o lower address/data bus for ex ternal memory expansion input p40 to p47 a8 to a15 output higher address bus for exte rnal memory expansion input p50 to p57 rd output strobe signal output for exte rnal memory read operation input p64 wr output strobe signal output for exter nal memory write operation input p65 wait input wait insertion on external memory access input p66 astb output strobe output that externa lly latches address information output to ports 4 and 5 for access to external memory input p67 ani0 to ani7 input a/d converter analog input input p20 to p27 av ref input a/d converter reference voltage input and positive power supply for port 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 2 pin functions user?s manual u15947ej2v0ud 51 2.2 description of pin functions 2.2.1 p00 to p06 (port 0) p00 to p06 function as a 7-bit i/o port. these pins also function as timer i/o, serial interface data i/o, clock i/o, and chip select input. the following operation modes can be specified in 1-bit units. (1) port mode p00 to p06 function as a 7-bit i/o port. p00 to p06 can be set to input or output in 1-bit units using port mode register 0 (pm0). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). (2) control mode p00 to p06 function as timer i/o, serial inte rface data i/o, clock i/o, and chip select input. (a) ti000, ti001 note these are the pins for inputting an external count clo ck to 16-bit timer/event counters 00 and 01 and are also for inputting a capture trigger signal to the captur e registers (cr000, cr010 or cr001, cr011) of 16-bit timer/event counters 00 and 01. (b) ti010, ti011 note these are the pins for inputting a capture trigger signal to the capture register (cr000 or cr001) of 16-bit timer/event counters 00 and 01. (c) to00, to01 note these are timer output pins. (d) si11 note this is a serial interface serial data input pin. (e) so11 note this is a serial interface serial data output pin. (f) sck11 note this is a serial interface serial clock i/o pin. (g) ssi11 note this is a serial interface chip select input pin. note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the
chapter 2 pin functions user?s manual u15947ej2v0ud 52 2.2.2 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. these pins also function as pins for ex ternal interrupt re quest input, serial interface data i/o, cl ock i/o, and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output in 1-bit units using port mode register 1 (pm1). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and timer i/o. (a) si10 this is a serial interface serial data input pin. (b) so10 this is a serial interface serial data output pin. (c) sck10 this is a serial interface serial clock i/o pin. (d) rxd0, rxd6 these are the serial data input pins of the asynchronous serial interface. (e) txd0, txd6 these are the serial data output pins of the asynchronous serial interface. (f) ti50 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 50. (g) to50, toh0, and toh1 these are timer output pins. (h) intp5 this is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.3 p20 to p27 (port 2) p20 to p27 function as an 8-bit input-only port. these pins also function as pins for a/d converter analog input. the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit input-only port. (2) control mode p20 to p27 function as a/d converter analog input pins (ani0 to ani7). when using these pins as analog input pins, see (5) ani0/p20 to ani7/p27 in 13.6 cautions for a/d converter .
chapter 2 pin functions user?s manual u15947ej2v0ud 53 2.2.4 p30 to p33 (port 3) p30 to p33 function as a 4-bit i/o port. these pins also function as pins for external in terrupt request input and timer i/o. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p33 function as a 4-bit i/o port. p30 to p33 can be set to input or output in 1-bit units using port mode register 3 (pm3). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p33 function as external interru pt request input pins and timer i/o pins. (a) intp1 to intp4 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti51 this is an external count clock input pin to 8-bit timer/event counter 51. (c) to51 this is a timer output pin. 2.2.5 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. these pins also function as address/data bus pins. the following operation modes can be specified. (1) port mode p40 to p47 function as an 8-bit i/o port. p40 to p47 can be set to input or output in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (pu4). (2) control mode p40 to p47 function as the pins for the lower address/data bus (ad0 to ad7) in external memory expansion mode. caution the external bus interface function cannot be used in (a1) grade products and (a2) grade products. 2.2.6 p50 to p57 (port 5) p50 to p57 function as an 8-bit i/o port. these pins also function as address bus pins. the following operation modes can be specified. (1) port mode p50 to p57 function as an 8-bit i/o port. p50 to p57 can be set to input or output in 1-bit units using port mode register 5 (pm5). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 5 (pu5). (2) control mode p50 to p57 function as the pins for the higher address bus (a8 to a15) in external memory expansion mode. caution the external bus interface function cannot be used in (a1) grade products and (a2) grade products.
chapter 2 pin functions user?s manual u15947ej2v0ud 54 2.2.7 p60 to p67 (port 6) p60 to p67 function as an 8-bit i/o port. these pins also function as control pins in ex ternal memory expansion mode. the following operation modes can be specified. (1) port mode p60 to p67 function as an 8-bit i/o port. p60 to p67 can be set to input port or output port in 1-bit units using port mode register 6 (pm6). p60 to p63 are n-ch open-drain pins. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. use of an on-chip pull-up resistor can be specified for p6 4 to p67 by pull-up resistor option register 6 (pu6). (2) control mode p64 to p67 function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. cautions 1. p66 functions as an i/o port if the externa l wait is not used in external memory expansion mode. 2. the external bus interface function cannot be used in (a1) grade products and (a2) grade products. 2.2.8 p70 to p77 (port 7) p70 to p77 function as an 8-bit i/o port. these pins also function as key interrupt input pins. the following operation modes can be specified in 1-bit units. (1) port mode p70 to p77 function as an 8-bit i/o port. p70 to p77 can be set to input or output in 1-bit units using port mode register 7 (pm7). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). (2) control mode p70 to p77 function as key interrupt input pins. 2.2.9 p120 (port 12) p120 functions as a 1-bit i/o port. this pin also func tions as a pin for external interrupt request input. the following operation modes can be specified. (1) port mode p120 functions as a 1-bit i/o port. p120 can be set to input or output using port mode register 12 (pm12). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). (2) control mode p120 functions as an external interrupt request input pin (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.10 p130 (port 13) p130 functions as a 1-bit output-only port.
chapter 2 pin functions user?s manual u15947ej2v0ud 55 2.2.11 p140 to p145 (port 14) p140 to p145 function as a 6-bit i/o port. these pins also function as external inte rrupt request inpu t, clock output, buzzer output, serial interface data i/o, cl ock i/o, busy input, and strobe output pins. the following operation modes can be specified in 1-bit units. (1) port mode p140 to p145 function as a 6-bit i/o port. p140 to p145 can be set to input or output in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). (2) control mode p140 to p145 function as external interrupt request input, clock output, buzzer output, se rial interface data i/o, clock i/o, busy input, and strobe output pins. (a) intp6, intp7 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) pcl this is a clock output pin. (c) buz this is a buzzer output pin. (d) sia0 this is a serial interface serial data input pin. (e) soa0 this is a serial interface serial data output pin. (f) scka0 this is a serial interface serial clock i/o pin. (g) busy0 this is a serial interface busy input pin. (h) stb0 this is a serial interface strobe output pin. 2.2.12 av ref this is the a/d converter reference voltage input pin. when the a/d converter is not used, connect this pin directly to ev dd or v dd note . note connect port 2 directly to ev dd when it is used as a digital port. 2.2.13 av ss this is the a/d converter ground potenti al pin. even when the a/d converter is not used, always use this pin with the same potential as the ev ss pin or v ss pin.
chapter 2 pin functions user?s manual u15947ej2v0ud 56 2.2.14 reset this is the active-low system reset input pin. 2.2.15 regc this is the pin for connecting the capacitor for the regul ator. when using the regulator, connect this pin to v ss via a capacitor (1
chapter 2 pin functions user?s manual u15947ej2v0ud 57 2.3 pin i/o circuits and recomme nded connection of unused pins table 2-2 shows the types of pin i/o circuits and the recommended connections of unused pins. see figure 2-1 for the configuration of the i/o circuit of each type. table 2-2. pin i/o circuit types (1/2) note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the
chapter 2 pin functions user?s manual u15947ej2v0ud 58 table 2-2. pin i/o circuit types (2/2) note connect port 2 directly to ev dd when it is used as a digital port. pin name i/o circuit type i/o recommended connection of unused pins p130 3-c output leave open. p140/pcl/intp6 p141/buz/busy0/intp7 p142/scka0 p143/sia0 8-a p144/soa0 p145/stb 5-a i/o input: independently connect to ev dd or ev ss via a resistor. output: leave open. reset 2 ? ? ?
chapter 2 pin functions user?s manual u15947ej2v0ud 59 figure 2-1. pin i/o circuit list (1/2) type 3-c type 2 type 8-a type 5-a type 9-c schmitt-triggered input with hysteresis characteristics in pullup enable data output disable ev dd p-ch v dd p-ch in/out n-ch ev dd p-ch n-ch data out in comparator v ref (threshold voltage) av ss p-ch n-ch input enable + ? pullup enable data output disable input enable ev dd p-ch v dd p-ch in/out n-ch data output disable in/out n-ch type 13-r
chapter 2 pin functions user?s manual u15947ej2v0ud 60 figure 2-1. pin i/o circuit list (2/2) type 13-v type 13-s type 13-w type 16 data output disable in/out n-ch ev dd mask option ? ? ? ? ? ? ? ? ? ? ? ?
user?s manual u15947ej2v0ud 61 chapter 3 cpu architecture 3.1 memory space 78k0/kf1 products can each access a 64 kb memory spac e. figures 3-1 to 3-5 show the memory maps. caution regardless of the internal memory capacity, the initial valu es of the internal memory size switching register (ims) and inte rnal expansion ram size switching register (ixs) of all 78k0/kf1 products are fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. table 3-1. set values of internal memo ry size switching register (ims) and internal expansion ram si ze switching register (ixs) ims ixs
chapter 3 cpu architecture user?s manual u15947ej2v0ud 62 figure 3-1. memory map (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 63 figure 3-2. memory map (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 64 figure 3-3. memory map (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 65 figure 3-4. memory map (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 66 figure 3-5. memory map (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 67 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/kf1 products incorporate internal rom (ma sk rom or flash memory), as shown below. table 3-2. intern al rom capacity internal rom part number structure capacity
chapter 3 cpu architecture user?s manual u15947ej2v0ud 68 (2) callt instruction table area the 64-byte area 0040h to 007fh can st ore the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subrout ine call with a 2-byte ca ll instruction (callf). 3.1.2 internal da ta memory space 78k0/kf1 products incorporate the following rams. (1) internal high-speed ram the internal high-speed ram is allocated to the area fb00h to feffh in a 1024 ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 69 3.1.4 data memory addressing addressing refers to the method of specifying the addre ss of the instruction to be ex ecuted next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0/kf1, based on operability and other considerations. for areas contai ning data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-6 to 3-10 show correspondence between data memory and addressing. for details of each addressing mode, see 3.4 operand address addressing . figure 3-6. correspondence between data memory and addressing (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 70 figure 3-7. correspondence between data memory and addressing (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 71 figure 3-8. correspondence between data memory and addressing (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 72 figure 3-9. correspondence between data memory and addressing (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 73 figure 3-10. correspondence between data memory and addressing (
chapter 3 cpu architecture user?s manual u15947ej2v0ud 74 3.2 processor registers the 78k0/kf1 products incorporate t he following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented ac cording to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-11. format of program counter 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are re stored upon execution of the retb , reti and pop psw instructions. reset input sets the psw to 02h. figure 3-12. format of program status word 7 0 psw ie z rbs1 ac rbs0 0 isp cy (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (d i) state, and all maskable interrupts are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgment is controlled with an in-service priority flag (isp), an inte rrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases.
chapter 3 cpu architecture user?s manual u15947ej2v0ud 75 (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates th e register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable ma skable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (pr0l, pr0h, pr1l, pr1h) (see 19.3 (3) priority specification flag registers (pr0l, pr0h, pr1l, pr1h) ) cannot be acknowledged. actual interrupt request acknowledgment is controlled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-13. format of stack pointer 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-14 and 3-15. caution since reset input makes the sp contents undefi ned, be sure to initia lize the sp before using the stack.
chapter 3 cpu architecture user?s manual u15947ej2v0ud 76 figure 3-14. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh
chapter 3 cpu architecture user?s manual u15947ej2v0ud 77 figure 3-15. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh
chapter 3 cpu architecture user?s manual u15947ej2v0ud 78 3.2.2 general-purpose registers general-purpose registers are mapped at particular a ddresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are se t by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program ca n be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-16. configuration of general-purpose registers (a) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h
chapter 3 cpu architecture user?s manual u15947ej2v0ud 79 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh area. special function registers can be manipulated like gener al-purpose registers, using operation, transfer and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? ? ? ? ? ? ? ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 80 table 3-5. special function register list (1/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port register 0 p0 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 81 table 3-5. special function register list (2/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff2ch port mode register 12 pm12 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 82 table 3-5. special function register list (3/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff6bh 8-bit timer mode control register 50 tmc50 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 83 table 3-5. special function register list (4/4) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffb2h ffb3h 16-bit timer capture/compare register 001 note 1 cr001 r/w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 84 3.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the num ber of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for deta ils of instructions, refer to 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displ acement value: jdisp8) of an instruction code to the start address of the following instruction is transferre d to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? + ? + +
chapter 3 cpu architecture user?s manual u15947ej2v0ud 85 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branc hed to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0
chapter 3 cpu architecture user?s manual u15947ej2v0ud 86 3.3.3 table indirect addressing [function] table contents (branch destinat ion address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation co de are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address stored in the me mory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 3.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are trans ferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture user?s manual u15947ej2v0ud 87 3.4 operand address addressing the following methods are available to specify the regi ster and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/kf1 instruction word s, the following instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically employ ed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit
chapter 3 cpu architecture user?s manual u15947ej2v0ud 88 3.4.2 register addressing [function] the general-purpose register to be specified is accesse d as an operand with the register bank select flags (rbs0 to rbs1) and the register specify co des (rn and rpn) of an operation code. register addressing is carried out when an instruction wi th the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1100010 register specify code incw de; when selecting de register pair as rp operation code 1 0000100 register specify code
chapter 3 cpu architecture user?s manual u15947ej2v0ud 89 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 1 0 0 0 1 1 1 0 op code 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
chapter 3 cpu architecture user?s manual u15947ej2v0ud 90 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addre ssing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and comp are and capture registers of the timer/event counter are mapped in this area, allowing sfrs to be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is cleared to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to the [illustration] . [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] mov 0fe30h, a; when transferring valu e of a register to saddr (fe30h) operation code 1 1110010 op c ode 0 0110000 30h (s addr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset
chapter 3 cpu architecture user?s manual u15947ej2v0ud 91 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff 00h to ffcfh and ffe0h to ffffh. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special func tion register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 1 1 1 1 0 1 1 0 op code 0 0 1 0 0 0 0 0 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture user?s manual u15947ej2v0ud 92 3.4.6 register indirect addressing [function] register pair contents specified by a register pair spec ify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all the memory spaces. [operand format] identifier description ?
chapter 3 cpu architecture user?s manual u15947ej2v0ud 93 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the content s of the base register, that is , the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? + + +
chapter 3 cpu architecture user?s manual u15947ej2v0ud 94 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perf ormed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? ++ + +
chapter 3 cpu architecture user?s manual u15947ej2v0ud 95 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] in the case of push de (saving de register) operation code 1 0 1 1 0 1 0 1 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh
user?s manual u15947ej2v0ud 96 chapter 4 port functions 4.1 port functions there are two types of pin i/o buffer power supplies: av ref and ev dd . the relationship between these power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies power supply corresponding pins av ref p20 to p27 ev dd port pins other than p20 to p27 78k0/kf1 products are provided with the ports shown in figure 4-1, which ena ble variety of control operations. the functions of each port are shown in table 4-2. in addition to the function as digi tal i/o ports, these ports have several alte rnate functions. for details of the alternate functions, see chapter 2 pin functions . figure 4-1. port types port 2 p20 p27 port 3 p30 p33 port 5 p50 p57 port 0 p00 p06 port 1 p10 p17 port 4 p40 p47 port 6 p60 p67 port 7 p70 p77 p120 port 12 port 14 p140 p145 p130 port 13
chapter 4 port functions user?s manual u15947ej2v0ud 97 table 4-2. port functions (1/2) pin name i/o function after reset alternate function p00 ti000 p01 ti010/to00 p02 so11 note p03 si11 note p04 sck11 note p05 ssi11 note /ti001 note p06 i/o port 0. 7-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti011 note /to01 note p10 sck10/txd0 p11 si10/rxd0 p12 so10 p13 txd6 p14 rxd6 p15 toh0 p16 toh1/intp5 p17 i/o port 1. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ti50/to50 p20 to p27 input port 2. 8-bit input-only port. input ani0 to ani7 p30 to p32 intp1 to intp3 p33 i/o port 3. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input intp4/ti51/to51 p40 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input ad0 to ad7 p50 to p57 i/o port 5. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input a8 to a15 note so11, si11, sck11, ssi11 , ti001, ti011, and to01 are available only in the
chapter 4 port functions user?s manual u15947ej2v0ud 98 table 4-2. port functions (2/2) pin name i/o function after reset alternate function p60 to p63 n-ch open-drain i/o port. use of an on-chip pull-up resistor can be specified by a mask option only for mask rom versions. ? ? ? ?
chapter 4 port functions user?s manual u15947ej2v0ud 99 4.2.1 port 0 port 0 is a 7-bit i/o port with an output latch. port 0 c an be set to the input mode or output mode in 1-bit units using port mode register 0 (pm0). when the p00 to p06 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0). this port can also be used for timer i/o , serial interface data i/o, and clock i/o. reset input sets port 0 to input mode. figures 4-2 to 4-5 show block diagrams of port 0. caution when p02/so11 note , p03/si11 note , and p04/sck11 note are used as general-purpose ports, do not write to serial clock selection register 11 (csic11). figure 4-2. block diagra m of p00, p03, and p05 p00/ti000, p03/si11 note , p05/ssi11 note /ti001 note wr pu rd wr port wr pm pu00, pu03, pu05 alternate function output latch (p00, p03, p05) pm00, pm03, pm05 ev dd p-ch selector internal bus pu0 pm0 note available only in the : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 100 figure 4-3. block diagram of p01 and p06 p01/ti010/to00, p06/ti011 note /to01 note wr pu rd wr port wr pm pu01, pu06 alternate function output latch (p01, p06) pm01, pm06 alternate function ev dd p-ch selector internal bus pu0 pm0 note available only in the : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 101 figure 4-4. block diagram of p02 p02/so11 note wr pu rd wr port wr pm pu02 output latch (p02) pm02 alternate function ev dd p-ch selector internal bus pu0 pm0 note available only in the : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 102 figure 4-5. block diagram of p04 p04/sck11 note wr pu rd wr port wr pm pu04 alternate function output latch (p04) pm04 alternate function ev dd p-ch selector internal bus pu0 pm0 note available only in the : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 103 4.2.2 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). this port can also be used for external interrupt requ est input, serial interfac e data i/o, clock i/o, and timer i/o. reset input sets port 1 to input mode. figures 4-6 to 4-10 show block diagrams of port 1. caution when p10/sck10/txd0, p11/si10/rxd0, and p12/so10 are used as general-purpose ports, do not write to serial clock selection register 10 (csic10). figure 4-6. block diagram of p10 p10/sck10/txd0 wr pu rd wr port wr pm pu10 alternate function output latch (p10) pm10 alternate function ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 104 figure 4-7. block diagram of p11 and p14 p11/si10/rxd0, p14/rxd6 wr pu rd wr port wr pm pu11, pu14 alternate function output latch (p11, p14) pm11, pm14 ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 105 figure 4-8. block diagram of p12 and p15 p12/so10 p15/toh0 wr pu rd wr port wr pm pu12, pu15 output latch (p12, p15) pm12, pm15 alternate function ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 106 figure 4-9. block diagram of p13 p13/txd6 wr pu rd wr port wr pm pu13 output latch (p13) pm13 alternate function ev dd p-ch internal bus selector pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 107 figure 4-10. block diagram of p16 and p17 p16/toh1/intp5, p17/ti50/to50 wr pu rd wr port wr pm pu16, pu17 alternate function output latch (p16, p17) pm16, pm17 alternate function ev dd p-ch selector internal bus pu1 pm1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 108 4.2.3 port 2 port 2 is an 8-bit input-only port. this port can also be used for a/d converter analog input. figure 4-11 shows a block diagram of port 2. figure 4-11. block di agram of p20 to p27 rd a/d converter p20/ani0 to p27/ani7 internal bus rd: read signal
chapter 4 port functions user?s manual u15947ej2v0ud 109 4.2.4 port 3 port 3 is a 4-bit i/o port with an output latch. port 3 c an be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input. reset input sets port 3 to input mode. figures 4-12 and 4-13 show block diagrams of port 3. figure 4-12. block di agram of p30 to p32 p30/intp1 to p32/intp3 wr pu rd wr port wr pm pu30 to pu32 alternate function output latch (p30 to p32) pm30 to pm32 ev dd p-ch selector internal bus pu3 pm3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 110 figure 4-13. blo ck diagram of p33 p33/intp4/ti51/to51 wr pu rd wr port wr pm pu33 alternate function output latch (p33) pm33 alternate function ev dd p-ch selector internal bus pu3 pm3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 111 4.2.5 port 4 port 4 is an 8-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (pu4). this port can also be used as an address/data bus in external memory expansion mode. reset input sets port 4 to input mode. figure 4-14 shows a block diagram of port 4. figure 4-14. block diag ram of p40 to p47 rd p40/ad0 to p47/ad7 p-ch wr pu wr port wr pm pu40 to pu47 output latch (p40 to p47) pm40 to pm47 alternate function selector selector memory expansion mode register (mem) ev dd alternate function pu4 pm4 internal bus pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 112 4.2.6 port 5 port 5 is an 8-bit i/o port with an output latch. port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (pm5). use of an on-chip pull- up resistor can be specified in 1-bit units using pull-up resistor option register 5 (pu5). this port can also be used as an address bus in external memory expansion mode. reset input sets port 5 to input mode. figure 4-15 shows a block diagram of port 5. figure 4-15. block diag ram of p50 to p57 rd p50/a8 to p57/a15 p-ch wr pu wr port wr pm pu50 to pu57 output latch (p50 to p57) pm50 to pm57 alternate function selector selector ev dd pu5 pm5 memory expansion mode register (mem) internal bus pu5: pull-up resistor option register 5 pm5: port mode register 5 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 113 4.2.7 port 6 port 6 is an 8-bit i/o port with an output latch. port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (pm6). this port has the following functions for pull-up resistor s. these functions differ depending on the higher 4 bits/lower 4 bits of the port, and whether the product is a mask rom version or a flash memory version. table 4-4. pull-up resistor of port 6 higher 4 bits (pins p64 to p67) lower 4 bits (pins p60 to p63) mask rom version an on-chip pull-up resistor can be specified in 1-bit units by mask option flash memory version an on-chip pull-up resistor can be connected in 1-bit units by pu6 on-chip pull-up resistors are not provided pu6: pull-up resistor option register 6 the p60 to p63 pins are n-ch open-drain pins. the p64 to p67 pins can also be used for the control signa l output function in external memory expansion mode. reset input sets port 6 to input mode. figures 4-16 to 4-18 show block diagrams of port 6. caution p66 can be used as an i/o por t when an external wait is not used in external memory expansion mode. figure 4-16. block diag ram of p60 to p63 rd p60 to p63 wr port wr pm output latch (p60 to p63) pm60 to pm63 selector ev dd mask option resistor ? ? ? ? ? ? ? ? ? ? : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 114 figure 4-17. block diagra m of p64, p65, and p67 rd p64/rd, p65/wr, p67/astb p-ch wr pu wr port wr pm pu64, pu65, pu67 output latch (p64, p65, p67) pm64, pm65, pm67 alternate function selector selector ev dd pu6 pm6 memory expansion mode register (mem) internal bus pu6: pull-up resistor option register 6 pm6: port mode register 6 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 115 figure 4-18. blo ck diagram of p66 rd p66/wait p-ch wr pu wr port wr pm pu66 output latch (p66) pm66 selector selector ev dd alternate function pu6 pm6 internal bus memory expansion mode register (mem) pu6: pull-up resistor option register 6 pm6: port mode register 6 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 116 4.2.8 port 7 port 7 is an 8-bit i/o port with an output latch. port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (pm7). when the p70 to p77 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (pu7). this port can also be used for key return input. reset input sets port 7 to input mode. figure 4-19 shows a block diagram of port 7. figure 4-19. block di agram of p70 to p77 p70/kr0 to p77/kr7 wr pu rd wr port wr pm pu70 to pu77 alternate function output latch (p70 to p77) pm70 to pm77 ev dd p-ch selector internal bus pu7 pm7 pu7: pull-up resistor option register 7 pm7: port mode register 7 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 117 4.2.9 port 12 port 12 is a 1-bit i/o port with an output latch. port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an inpu t port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used for external interrupt input. reset input sets port 12 to input mode. figure 4-20 shows a block diagram of port 12. figure 4-20. blo ck diagram of p120 p120/intp0 wr pu rd wr port wr pm pu120 alternate function output latch (p120) pm120 ev dd p-ch selector internal bus pu12 pm12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 118 4.2.10 port 13 port 13 is a 1-bit output-only port. figure 4-21 shows a block diagram of port 13. figure 4-21. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus rd: read signal wr : write signal remark when reset is effected, p130 outputs a low level. if p130 is set to output a high level immediately after reset is released, the output signal of p130 can be dummy-output as the reset signal to the cpu.
chapter 4 port functions user?s manual u15947ej2v0ud 119 4.2.11 port 14 port 14 is a 6-bit i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 to p1 45 pins are used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). this port can also be used for external interrupt requ est input, serial interface data i/o, clock i/o, busy input, buzzer output, and clock output. reset input sets port 14 to input mode. figures 4-22 to 4-25 show block diagrams of port 14. figure 4-22. block di agram of p140 and p141 p140/pcl/intp6, p141/buz/busy0/intp7 wr pu rd wr port wr pm pu140, pu141 alternate function output latch (p140, p141) pm140, pm141 alternate function ev dd p-ch selector internal bus pu14 pm14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 120 figure 4-23. blo ck diagram of p142 p142/scka0 wr pu rd wr port wr pm pu142 alternate function output latch (p142) pm142 alternate function ev dd p-ch selector internal bus pu14 pm14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 121 figure 4-24. blo ck diagram of p143 p143/sia0 wr pu rd wr port wr pm pu143 alternate function output latch (p143) pm143 ev dd p-ch selector internal bus pu14 pm14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 122 figure 4-25. block di agram of p144 and p145 p144/soa0, p145/stb0 wr pu rd wr port wr pm pu144, pu145 output latch (p144, p145) pm144, pm145 alternate function ev dd p-ch selector internal bus pu14 pm14 pu14: pull-up resistor option register 14 pm14: port mode register 14 rd: read signal wr : write signal
chapter 4 port functions user?s manual u15947ej2v0ud 123 4.3 registers controlling port function port functions are controlled by the following three types of registers. ? ? ?
chapter 4 port functions user?s manual u15947ej2v0ud 124 table 4-5. settings of port mode register a nd output latch when using alternate function (1/2) notes 1. so11, si11, sck11, ssi11 , ti001, ti011, and to01 ar e available only in the
chapter 4 port functions user?s manual u15947ej2v0ud 125 table 4-5. settings of port mode register a nd output latch when using alternate function (2/2) alternate function pin name function name i/o pm
chapter 4 port functions user?s manual u15947ej2v0ud 126 (2) port registers (p0 to p7, p12 to p14) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the value of the output latch is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h (but p2 is undefined). figure 4-27. format of port register 7 0 symbol p0 6 p06 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address ff00h after reset 00h (output latch) r/w r/w 7 p17 p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 ff01h 00h (output latch) r/w r 7 p27 p2 6 p26 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 ff02h undefined 7 0 p3 6 0 5 0 4 0 3 p33 2 p32 1 p31 0 p30 ff03h 00h (output latch) r/w 7 p47 p4 6 p46 5 p45 4 p44 3 p43 2 p42 1 p41 0 p40 ff04h 00h (output latch) r/w 7 p57 p5 6 p56 5 p55 4 p54 3 p53 2 p52 1 p51 0 p50 ff05h 00h (output latch) r/w 7 p67 p6 6 p66 5 p65 4 p64 3 p63 2 p62 1 p61 0 p60 ff06h 00h (output latch) r/w 7 p77 p7 6 p76 5 p75 4 p74 3 p73 2 p72 1 p71 0 p70 ff07h 00h (output latch) r/w 7 0 p12 6 0 5 0 4 0 3 0 2 0 1 0 0 p120 ff0ch 00h (output latch) r/w 7 0 p13 6 0 5 0 4 0 3 0 2 0 1 0 0 p130 ff0dh 00h (output latch) r/w 7 0 p14 6 0 5 p145 4 p144 3 p143 2 p142 1 p141 0 p140 ff0eh 00h (output latch) r/w m = 0 to 7, 12 to 14; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level
chapter 4 port functions user?s manual u15947ej2v0ud 127 (3) pull-up resistor option registers (p u0, pu1, pu3 to pu7, pu12, and pu14) these registers specify whether the on-ch ip pull-up resistors of p00 to p06, p 10 to p17, p30 to p33, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p120, or p140 to p145 are to be used or not. on-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified. on-chip pull-up resistors cannot be connected for bits set to output mode and bits used as alternate-function output pins, regardless of the setti ngs of pu0, pu1, pu3 to pu7, pu12, and pu14. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. caution use of a pull-up resistor can be specified for p60 to p63 pins by a mask option only in the mask rom versions. figure 4-28. format of pull-up resistor option register 7 0 symbol pu0 6 pu06 5 pu05 4 pu04 3 pu03 2 pu02 1 pu01 0 pu00 address ff30h after reset 00h r/w r/w 7 pu17 pu1 6 pu16 5 pu15 4 pu14 3 pu13 2 pu12 1 pu11 0 pu10 ff31h 00h r/w 7 0 pu3 6 0 5 0 4 0 3 pu33 2 pu32 1 pu31 0 pu30 ff33h 00h r/w 7 pu47 pu4 6 pu46 5 pu45 4 pu44 3 pu43 2 pu42 1 pu41 0 pu40 ff34h 00h r/w 7 pu57 pu5 6 pu56 5 pu55 4 pu54 3 pu53 2 pu52 1 pu51 0 pu50 ff35h 00h r/w 7 pu67 pu6 6 pu66 5 pu65 4 pu64 3 0 2 0 1 0 0 0 ff36h 00h r/w 7 pu77 pu7 6 pu76 5 pu75 4 pu74 3 pu73 2 pu72 1 pu71 0 pu70 ff37h 00h r/w 7 0 pu12 6 0 5 0 4 0 3 0 2 0 1 0 0 pu120 ff3ch 00h r/w 7 0 pu14 6 0 5 pu145 4 pu144 3 pu143 2 pu142 1 pu141 0 pu140 ff3eh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 7, 12, 14; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected
chapter 4 port functions user?s manual u15947ej2v0ud 128 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. caution in the case of a 1- bit memory manipulation instruction, al though a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as i nput are undefined, even for bits other than the manipulated bit. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instru ction, and the output latch contents are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is cleared by reset. (2) input mode the pin level is read and an operation is performed on its contents. the result of the operat ion is written to the output latch, but since the output buffer is off, the pin status does not change.
user?s manual u15947ej2v0ud 129 chapter 5 external bus interface 5.1 external bus interface the external bus interface connects external devices to areas other than the internal rom, ram, and sfr areas. connection of external devices uses ports 4 to 6. ports 4 to 6 control address/data, re ad/write strobe, wait, address strobe, etc. the external bus interface is usable only when the x1 clock is selected as the cpu clock. caution the external bus interface function cannot be used in (a1) grade products and (a2) grade products. table 5-1. pin functions in ex ternal memory expansion mode pin function when external device is connected name function alternate function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 5-2. state of ports 4 to 6 pins in external memo ry expansion mode port 4 port 5 port 6 external port expansion mode 0 to 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 single-chip mode port port port 256-byte expansion mode address/data port port rd, wr, wait, astb 4 kb expansion mode address/data address port port rd, wr, wait, astb 16 kb expansion mode address/data address port port rd, wr, wait, astb full-address mode address/data address port rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as a port in all modes.
chapter 5 external bus interface user?s manual u15947ej2v0ud 130 the memory maps when the external bus interface is used are as follows. figure 5-1. memory map when us ing external bus interface (1/2) (a) memory map of
chapter 5 external bus interface user?s manual u15947ej2v0ud 131 figure 5-1. memory map when us ing external bus interface (2/2) (c) memory map of
chapter 5 external bus interface user?s manual u15947ej2v0ud 132 5.2 registers controlling external bus interface the external bus interface is controll ed by the following two registers. ? ?
chapter 5 external bus interface user?s manual u15947ej2v0ud 133 note when the cpu accesses the external memory expansion area, the lower bits of the address to be accessed are output to the specified pins (except in the full-address mode). figure 5-3. pins specified for address (with
chapter 5 external bus interface user?s manual u15947ej2v0ud 134 (2) memory expansion wa it setting register (mm) mm sets the number of waits. mm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 5-4. format of memory expa nsion wait setting register (mm) address: fff8h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 mm 0 0 pw1 pw0 0 0 0 0 pw1 pw0 wait control 0 0 no wait 0 1 wait (one wait state inserted) 1 0 setting prohibited 1 1 wait control by external wait pin cautions 1. to control wait with external wait pi n, be sure to set wait/p66 pin to input mode (set bit 6 (pm66) of port mode register 6 (pm6) to 1). 2. if the external wait pin is not used fo r wait control, the wait/p66 pin can be used as an i/o port pin.
chapter 5 external bus interface user?s manual u15947ej2v0ud 135 5.3 external bus interface function timing timing control signal output pins in the exter nal memory expansion mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is ou tput in data read and instruction fetch from external memory. during internal memory read, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. t he write strobe signal is output in data write to external memory. during internal memory write, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an i/o port. during internal memory access, the ex ternal wait signal is ignored. (4) astb pin (alterna te function: p67) address strobe signal output pin. the address stro be signal is output regardless of data access and instruction fetch from external memory. during internal memory access, t he address strobe signal is output. (5) ad0 to ad7, a8 to a15 pins (alternate function: p40 to p47, p50 to p57) address/data signal output pins. valid signal is outpu t or input during data accesses and instruction fetches from external memory. these signals change even during internal memory access (output values are undefined). the timing charts are shown in figures 5-5 to 5-8.
chapter 5 external bus interface user?s manual u15947ej2v0ud 136 figure 5-5. instruction fetc h from external memory (a) no wait (pw1, pw0 = 0, 0) setting rd astb ad0 to ad7 a8 to a15 lower address instruction code higher address (b) wait (pw1, pw0 = 0, 1) setting rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address instruction code higher address (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 wait lower address instruction code higher address
chapter 5 external bus interface user?s manual u15947ej2v0ud 137 figure 5-6. external memory read timing (a) no wait (pw1, pw0 = 0, 0) setting rd astb ad0 to ad7 a8 to a15 lower address read data higher address (b) wait (pw1, pw0 = 0, 1) setting rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address read data higher address (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 wait lower address read data higher address
chapter 5 external bus interface user?s manual u15947ej2v0ud 138 figure 5-7. external memory write timing (a) no wait (pw1, pw0 = 0, 0) setting wr astb ad0 to ad7 a8 to a15 lower address write data higher address hi-z (b) wait (pw1, pw0 = 0, 1) setting wr astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address write data higher address hi-z (c) external wait (pw1, pw0 = 1, 1) setting wr astb ad0 to ad7 a8 to a15 wait lower address write data higher address hi-z
chapter 5 external bus interface user?s manual u15947ej2v0ud 139 figure 5-8. external memory read modify write timing (a) no wait (pw1, pw0 = 0, 0) setting read data write data higher address hi-z lower address rd astb ad0 to ad7 a8 to a15 wr (b) wait (pw1, pw0 = 0, 1) setting rd astb ad0 to ad7 a8 to a15 hi-z wr write data higher address internal wait signal (1-clock wait) read data lower address (c) external wait (pw1, pw0 = 1, 1) setting wait hi-z rd astb ad0 to ad7 a8 to a15 wr write data higher address read data lower address remark the read-modify-write timing is that of an operatio n when a bit manipulation instruction is executed.
chapter 5 external bus interface user?s manual u15947ej2v0ud 140 5.4 example of connection with memory an example of connecting the
user?s manual u15947ej2v0ud 141 chapter 6 clock generator 6.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three syst em clock oscillator s are available. ? ? ?
chapter 6 clock generator user?s manual u15947ej2v0ud 142 figure 6-1. block diagra m of clock generator x1 x2 f xp f xt frc xt1 xt2 f x 2 2 stop mstop f x 2 3 f x 2 4 f x 2 4 rstop css pcc2 cls mcm0 mcs cls mcc osts1 osts0 osts2 1/2 3 most 16 most 15 most 14 most 13 most 11 c p u f r f x pcc1 pcc0 x1 oscillator internal bus ring-osc mode register (rcm) main osc control register (moc) internal bus ring-osc oscillator mask option 1: cannot be stopped 0: can be stopped cpu clock (f cpu ) controller processor clock control register (pcc) main clock mode register (mcm) x1 oscillation stabilization time counter oscillation stabilization time select register (osts) oscillation stabilization time counter status register (ostc) clock to peripheral hardware prescaler operation clock switch 8-bit timer h1, watchdog timer prescaler prescaler selector subsystem clock oscillator watch clock, clock output function f cpu control signal
chapter 6 clock generator user?s manual u15947ej2v0ud 143 6.3 registers controlling clock generator the following six registers are used to control the clock generator. ? ? ? ? ? ?
chapter 6 clock generator user?s manual u15947ej2v0ud 144 figure 6-2. format of processor clock control register (pcc) address: fffbh after reset: 00h r/w note 1 symbol <7> <6> <5> <4> 3 2 1 0 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc control of x1 oscillator operation note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock f eedback resistor selection 0 on-chip feedback resistor used 1 on-chip feedback resistor not used note 3 cls cpu clock status 0 x1 input clock or ring-osc clock 1 subsystem clock notes 1. bit 5 is read-only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the x1 oscillator operation. when the cpu is operating on the ring-o sc clock, use bit 7 (mstop) of the main osc control register (moc) to stop the x1 oscillator operation (this cannot be set by mcc). a stop instruction should not be used. 3. this bit can be set to 1 only when the subsystem clock is not used. 4. be sure to switch css from 1 to 0 when bits 1 (mcs) and 0 (mcm0) of the main clock mode register (mcm) are 1. caution be sure to clear bit 3 to 0. cpu clock (f cpu ) selection css note 4 pcc2 pcc1 pcc0 mcm0 = 0 mcm0 = 1 0 0 0 f x f r f xp 0 0 1 f x /2 f r /2 f xp /2 0 1 0 f x /2 2 f r /2 2 f xp /2 2 0 1 1 f x /2 3 f r /2 3 f xp /2 3 0 1 0 0 f x /2 4 f r /2 4 f xp /2 4 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 f xt /2 other than above setting prohibited
chapter 6 clock generator user?s manual u15947ej2v0ud 145 remarks 1. mcm0: bit 0 of main clock mode register (mcm) 2. f x : main system clock oscillation frequency (x1 input clock oscillation frequency or ring-osc clock oscillation frequency) 3. f r : ring-osc clock oscillation frequency 4. f xp : x1 input clock oscillation frequency 5. f xt : subsystem clock oscillation frequency the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k0/kf1. therefor e, the relationship between the cpu clock (f cpu ) and minimum instruction execution time is as shown in the table 6-2. table 6-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu cpu clock (f cpu ) x1 input clock note (at 10 mhz operation) ring-osc clock note (at 240 khz (typ.) operation) subsystem clock (at 32.768 khz operation) f x 0.2 ? ? ? ? ? ? ?
chapter 6 clock generator user?s manual u15947ej2v0ud 146 (3) main clock mode register (mcm) this register sets the cpu clo ck (x1 input clock/ring-osc clock). mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 6-4. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 2 <1> <0> mcm 0 0 0 0 0 0 mcs mcm0 mcs cpu clock status 0 operates with ring-osc clock 1 operates with x1 input clock mcm0 selection of clock supplied to cpu 0 ring-osc clock 1 x1 input clock note bit 1 is read-only. cautions 1. when ring-osc clo ck is selected as the clock to be supplied to the cpu, the divided clock of the ring-osc oscillator output (f x ) is supplied to the peripheral hardware (f x = 240 khz (typ.)). operation of the peripheral hard ware with ring-osc clock cannot be guaranteed. therefore, when ring-osc cl ock is selected as the clock supplied to the cpu, do not use peripheral hardwa re. in addition, stop the peripheral hardware before switching the clock supplied to the cp u from the x1 input clock to the ring-osc clock. note, however, th at the following peripheral hardware can be used when the cpu ope rates on the ring-osc clock. ? ? ? ?
chapter 6 clock generator user?s manual u15947ej2v0ud 147 (4) main osc control register (moc) this register selects the operat ion mode of the x1 input clock. this register is used to stop the x1 oscillator operation when the cpu is operating with the ring-osc clock. therefore, this register is valid only when t he cpu is operating with the ring-osc clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 6-5. format of main osc control register (moc) address: ffa2h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 mstop control of x1 oscillator operation 0 x1 oscillator operating 1 x1 oscillator stopped cautions 1. make sure that bit 1 (mcs) of the main clock mode register (mcm) is 0 before setting mstop. 2. to stop x1 oscillation when the cpu is operating on the subsystem clock, set bit 7 (mcc) of the processor clock control re gister (pcc) to 1 (setting by mstop is not possible).
chapter 6 clock generator user?s manual u15947ej2v0ud 148 (5) oscillation stabilization time c ounter status register (ostc) this is the status register of the x1 input clock oscillation stabilization time counter. if the ring-osc clock is used as the cpu clock, the x1 input clock o scillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, clock monitor, and wdt), the stop instruction, mstop = 1, and mcc = 1 clear ostc to 00h. figure 6-6. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status 1 0 0 0 0 2 11 /f xp min. (204.8 ?
chapter 6 clock generator user?s manual u15947ej2v0ud 149 (6) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stabilization wait time when stop mode is released. the wait time set by osts is valid only after stop mode is released with the x1 input clock selected as cpu clock. after stop mode is released with ring-osc selected as cpu clock, the oscillation stabilization time must be confirmed by ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 6-7. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 0 0 1 2 11 /f xp (204.8 ?
chapter 6 clock generator user?s manual u15947ej2v0ud 150 6.4 system clock oscillator 6.4.1 x1 oscillator the x1 oscillator oscillates with a crystal resonator or ceramic resonator (standard: 8.38 mhz, 10 mhz when regc pin is connected directly to v dd ) connected to the x1 and x2 pins. an external clock can be input to the x1 oscillator when the regc pin is connected directly to v dd . in this case, input the clock signal to the x1 pin and in put the inverse signal to the x2 pin. figure 6-8 shows examples of the exte rnal circuit of the x1 oscillator. figure 6-8. examples of extern al circuit of x1 oscillator (a) crystal, ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator external clock x1 x2 6.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock os cillator when the regc pin is connected directly to v dd . in this case, input the clock signal to the xt 1 pin and the inverse signal to the xt2 pin. figure 6-9 shows examples of external ci rcuit of the subsystem clock oscillator. figure 6-9. examples of external ci rcuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz xt1 xt2 external clock cautions are listed on the next page.
chapter 6 clock generator user?s manual u15947ej2v0ud 151 cautions 1. when using the x1 o scillator and subsystem clock oscilla tor, wire as follows in the area enclosed by the broken lines in the figure 6-10 to avoid an adverse effect from wiring capacitance.  keep the wiring length as short as possible.  do not cross the wiring with the other signal lines.  do not route the wiring near a signal line th rough which a high fluctuating current flows.  always make the ground point of the os cillator capacitor the same potential as v ss . do not ground the capacitor to a ground patter n through which a high current flows.  do not fetch signals from the oscillator. note that the subsystem clock oscillator is designed as a low- amplitude circuit for reducing power consumption. figure 6-10 shows examples of incorrect resonator connection. figure 6-10. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side.
chapter 6 clock generator user?s manual u15947ej2v0ud 152 figure 6-10. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. when x2 and xt1 are wired in paralle l, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning.
chapter 6 clock generator user?s manual u15947ej2v0ud 153 6.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operat ions and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect directly to ev dd or v dd xt2: leave open in this state, however, some current may leak via the on-chip feedback resist or of the subsystem clock oscillator when the x1 input clock and ring-osc clock stop. to mini mize leakage current, the above on-chip feedback resistor can be set not to be used via bit 6 (frc) of the processor clo ck control register (pcc). in this case also, connect the xt1 and xt2 pins as described above. figure 6-11. subsystem cl ock feedback resistor frc p-ch feedback resistor xt1 xt2 remark the feedback resistor is required to control the bias point of the o scillation waveform so that the bias point is in the middle of the power supply voltage. 6.4.4 ring-osc oscillator ring-osc oscillator is inco rporated in the 78k0/kf1. ?can be stopped by software? or ?cannot be stopped? can be selected by a mask option. the ring-osc clock always oscillates after reset release (240 khz (typ.)). 6.4.5 prescaler the prescaler generates various clocks by dividing the x1 o scillator output when the x1 input clock is selected as the clock to be supplied to the cpu. caution when the ring-osc clock is selected as the clock supplied to the cpu, the prescaler generates various clocks by dividing th e ring-osc oscillator output (f x = 240 khz (typ.)).
chapter 6 clock generator user?s manual u15947ej2v0ud 154 6.5 clock generator operation the clock generator generates the following clocks and cont rols the operation modes of the cpu, such as standby mode. ? ? ? ? ?
chapter 6 clock generator user?s manual u15947ej2v0ud 155 figure 6-12. timing diagram of cpu default start using ring-osc ring-osc clock (f r ) cpu clock x1 input clock (f xp ) operation stopped: 17/f r x1 oscillation stabilization time: 2 11 /f xp to 2 16 /f xp note reset ring-osc clock x1 input clock switched by software subsystem clock (f xt ) note check using the oscillation stabilization time counter status register (ostc). (a) when the reset signal is generated, bit 0 of the ma in clock mode register (mcm) is cleared to 0 and the ring-osc clock is set as the cpu clock. however, a clock is supplied to the cpu after 17 clocks of the ring-osc clock have elapsed after reset release (or cloc k supply to the cpu stops for 17 clocks). during the reset period, oscillation of the x1 input clock and ring-osc clock is stopped. (b) after reset release, the cpu clock can be switched fr om the ring-osc clock to the x1 input clock using bit 0 (mcm0) of the main clock mode register (mcm) after the x1 input clock oscillation stabilization time has elapsed. at this time, check the oscillation stabilizatio n time using the oscillati on stabilization time counter status register (ostc) bef ore switching the cpu clock. the cpu clock status can be checked using bit 1 (mcs) of mcm. (c) ring-osc can be set to stopped/oscillating using th e ring-osc mode register (rcm) when ?can be stopped by software? is selected for the ring-osc by a mask opti on, if the x1 input or sub system clock is used as the cpu clock. make sure that mcs is 1 at this time. (d) when ring-osc is used as the cpu clock, the x1 i nput clock can be set to stopped/oscillating using the main osc control register (moc). make sure that mcs is 0 at this time. when the subsystem clock is used as the cpu clock, w hether the x1 input clock stops or oscillates can be set by the processor clock control register (pcc). in addition, halt mode can be used during operation with the subsystem clock, but stop mode cannot be used (subsystem clock oscillation can not be stopped by the stop instruction). (e) select the x1 input clock oscillation stabilization time (2 11 /f xp , 2 13 /f xp , 2 14 /f xp , 2 15 /f xp , 2 16 /f xp ) using the oscillation stabilization time select register (o sts) when releasing stop mode while x1 input clock is being used as the cpu clock. in addition, when releasing stop mode while reset is released and ring-osc clock is being used as the cpu clock, check the x1 input cl ock oscillation stabilization time using the oscillation stabilization time counter status register (ostc).
chapter 6 clock generator user?s manual u15947ej2v0ud 156 a status transition diagram of this product is shown in figure 6-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscill ation status of each clock are shown in tables 6-3 and 6-4, respectively. figure 6-13. status transition diagram (1/4) (1) when ?ring-osc can be stopped by software? is selected by mask option (when subsystem clock is not used) status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt reset release interrupt interrupt halt instruction stop instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction halt instruction stop note 4 reset note 5 notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 3. when shifting from status 2 to stat us 1, make sure that mcs is 0. 4. when ?ring-osc can be stopped by software? is selected by a mask option, the watchdog timer stops operating in the halt and stop modes, regardle ss of the source clock of the watchdog timer. however, oscillation of ring-osc does not stop ev en in the halt and stop modes if rstop = 0. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator user?s manual u15947ej2v0ud 157 figure 6-13. status transition diagram (2/4) (2) when ?ring-osc can be stopped by software? is selected by mask option (when subsystem clock is used) halt note 4 interrupt interrupt interrupt interrupt interrupt interrupt interrupt halt instruction halt instruction stop instruction stop instruction stop instruction rstop = 0 rstop = 1 note 1 mcc = 0 css = 0 note 5 mcc = 1 css = 1 note 5 mcm0 = 0 mcm0 = 1 note 2 mstop = 1 note 3 mstop = 0 halt instruction halt instruction stop note 4 reset note 6 status 4 cpu clock: f xp f xp : oscillating f r : oscillation stopped status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating reset release interrupt halt instruction status 6 cpu clock: f xt f xp : oscillation stopped f r : oscillating/ oscillation stopped status 5 cpu clock: f xt f xp : oscillating f r : oscillating/ oscillation stopped notes 1. when shifting from status 3 to status 4, make sure that bit 1 (mcs) of the main clock mode register (mcm) is 1. 2. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 3. when shifting from status 2 to stat us 1, make sure that mcs is 0. 4. when ?ring-osc can be stopped by software? is se lected by a mask option, the clock supply to the watchdog timer is stopped after the halt or stop instruction has been executed, regardless of the setting of bit 0 (rstop) of the ring-osc mode regi ster (rcm) and bit 0 (mcm0) of the main clock mode register (mcm). 5. the operation cannot be shifted between subsyst em clock operation and ring-osc operation. 6. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator user?s manual u15947ej2v0ud 158 figure 6-13. status transition diagram (3/4) (3) when ?ring-osc cannot be stop ped? is selected by mask option (when subsystem clock is not used) status 3 cpu clock: f xp f xp : oscillating f r : oscillating halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 4 status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 2. when shifting from status 2 to stat us 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ?ring- osc cannot be stopped? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using t he tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an in ternal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator user?s manual u15947ej2v0ud 159 figure 6-13. status transition diagram (4/4) (4) when ?ring-osc cannot be stop ped? is selected by mask option (when subsystem clock is used) halt interrupt interrupt interrupt stop instruction mcm0 = 0 mcm0 = 1 note 1 halt instruction halt instruction stop note 3 reset note 5 interrupt stop instruction interrupt interrupt stop instruction mstop = 1 note 2 mstop = 0 halt instruction reset release mcc = 0 css = 0 note 4 mcc = 1 css = 1 note 4 interrupt interrupt halt instruction halt instruction status 3 cpu clock: f xp f xp : oscillating f r : oscillating status 2 cpu clock: f r f xp : oscillating f r : oscillating status 1 cpu clock: f r f xp : oscillation stopped f r : oscillating status 5 cpu clock: f xt f xp : oscillation stopped f r : oscillating status 4 cpu clock: f xt f xp : oscillating f r : oscillating notes 1. before shifting from status 2 to status 3 after reset and stop are released, check the x1 input clock oscillation stabilization time status using the oscillation stabilizati on time counter status register (ostc). 2. when shifting from status 2 to stat us 1, make sure that mcs is 0. 3. the watchdog timer operates using ring-osc even in stop mode if ?ring- osc cannot be stopped? is selected by a mask option. ring-osc division can be selected as the count source of 8-bit timer h1 (tmh1), so clear the watchdog timer using t he tmh1 interrupt request before watchdog timer overflow. if this processing is not performed, an in ternal reset signal is generated at watchdog timer overflow after stop instruction execution. 4. the operation cannot be shifted between subsyst em clock operation and ring-osc operation. 5. all reset sources (reset input, poc, lvi, clock monitor, and wdt)
chapter 6 clock generator user?s manual u15947ej2v0ud 160 table 6-3. relationship between operat ion clocks in each operation status x1 oscillator ring-osc oscillator note 2 prescaler clock supplied to peripherals status operation mode mstop = 0 mcc = 0 mstop = 1 mcc = 1 note 1 rstop = 0 rstop = 1 subsystem clock oscillator cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating stopped oscillating oscillating stopped oscillating note 4 ring-osc x1 notes 1. when ?cannot be stopped? is select ed for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) table 6-4. oscillation control fl ags and clock oscillation status x1 oscillator ring-osc oscillator rstop = 0 stopped oscillating mstop = 1 note rstop = 1 setting prohibited rstop = 0 oscillating mstop = 0 note rstop = 1 oscillating stopped rstop = 0 oscillating mcc = 1 note rstop = 1 stopped stopped rstop = 0 oscillating mcc = 0 note rstop = 1 oscillating stopped note setting x1 oscillator oscillating/stopped differs depending on the cpu clock used. ? ?
chapter 6 clock generator user?s manual u15947ej2v0ud 161 6.6 time required to switch between ring-osc clock and x1 input clock bit 0 (mcm0) of the main clock mode register (mcm) is us ed to switch between the ring-osc clock and x1 input clock. in the actual switching operation, s witching does not occur immediately after mcm0 rewrite; several instructions are executed using the pre-switch clock after switching mcm0 (see table 6-5 ). bit 1 (mcs) of mcm is used to judge that operation is per formed using either the ring-osc clock or x1 input clock. to stop the original clock after s witching the clock, wait for the num ber of clocks shown in table 6-5. table 6-5. maximum time required to switch between ring-osc clock and x1 input clock pcc time required for switching pcc2 pcc1 pcc0 x1
chapter 6 clock generator user?s manual u15947ej2v0ud 162 6.7 time required for cpu clock switchover the cpu clock can be switched using bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed immedi ately after rewriting to the pcc; operation continues on the pre-switchover clock for several instructions (see table 6-6 ). whether the system is operat ing on the x1 input clock (or ring-osc clock) or the subsystem clock can be ascertained using bit 5 (cls) of the pcc register. table 6-6. maximum time requi red for cpu clock switchover set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css p cc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1
chapter 6 clock generator user?s manual u15947ej2v0ud 163 6.8 clock switching flowchart and register setting 6.8.1 switching from ring-os c clock to x1 input clock figure 6-14. switching from ring-osc clock to x1 input clock (flowchart) ; f cpu = f r ; ring-osc oscillation ; ring-osc clock operation ; x1 oscillation ; oscillation stabilization time status register ; oscillation stabilization time f xp /2 16 mcm.1 (mcs) is changed from 0 to 1 ; x1 oscillation stabilization time status check x1 oscillation stabilization time has elapsed x1 oscillation stabilization time has not elapsed pcc = 00h rcm = 00h mcm = 00h moc = 00h ostc = 00h osts = 05h note ostc check note each processing after reset release pcc setting mcm.0
chapter 6 clock generator user?s manual u15947ej2v0ud 164 6.8.2 switching from x1 input clock to ring-osc clock figure 6-15. switching from x1 input clock to ring-osc clock (flowchart) mcm.1 (mcs) is changed from 1 to 0 ; ring-osc clock operation ; ring-osc oscillating? ring-osc clock operation ; x1 oscillation ; x1 input clock or ring-osc clock ; x1 input clock operation no: rstop = 0 yes: rstop = 1 pcc.7 (mcc) = 0 pcc.4 (css) = 0 mcm = 03h rcm.0 note (rstop) = 1? rstop = 0 mcm0
chapter 6 clock generator user?s manual u15947ej2v0ud 165 6.8.3 switching from x1 input clock to subsystem clock figure 6-16. switching from x1 input clock to subsystem clock (flowchart) mcs = 1 not changed. cls is changed from 0 to 1. ; subsystem clock operation subsystem clock operation ; x1 oscillation ; x1 input clock or ring-osc clock ; x1 input clock operation pcc.7 (mcc) = 0 pcc.4 (css) = 0 mcm = 03h css
chapter 6 clock generator user?s manual u15947ej2v0ud 166 6.8.4 switching from subsystem clock to x1 input clock figure 6-17. switching from subsystem clock to x1 input clock (flowchart) ; subsystem clock operation ; x1 oscillating? ; x1 oscillation enabled ; wait for x1 oscillation stabilization time ; x1 input clock operation cls is changed from 1 to 0. mcs = 1 not changed. x1 oscillation stabilization time elapsed x1 oscillation stabilization time not elapsed yes: x1 oscillation stopped no: x1 oscillating mcc
chapter 6 clock generator user?s manual u15947ej2v0ud 167 6.8.5 register settings the table below shows the statuses of the setting flags and status flags when each mode is set. table 6-7. clock and register setting setting flag status flag pcc register mcm register moc register rcm register pcc register mcm register f cpu mode mcc css mcm0 mstop rstop note 1 cls mcs ring-osc oscillating 0 0 1 0 0 0 1 x1 input clock note 2 ring-osc stopped 0 0 1 0 1 0 1 x1 oscillating 0 0 0 0 0 0 0 ring-osc clock x1 stopped 0 note 3 0 0 1 0 0 0 x1 oscillating, ring-osc oscillating 0 1 1 note 5 0 note 6 0 1 1 x1 stopped, ring-osc oscillating 1 1 1 note 5 0 note 6 0 1 1 x1 oscillating, ring-osc stopped 0 1 1 note 5 0 note 6 1 1 1 subsystem clock note 4 x1 stopped, ring-osc stopped 1 1 1 note 5 0 note 6 1 1 1 notes 1. valid only when ?clock can be stopped by software? is selected for ring-osc by a mask option. 2. do not set mcc = 1 or mstop = 1 during x1 input clock operation (even if mcc = 1 or mstop = 1 is set, the x1 oscillation does not stop). 3. do not set mcc = 1 during ring-osc operation (even if mcc = 1 is set, the x1 oscillation does not stop). to stop x1 oscillation during ring-osc operation, use mstop. 4. shifting to subsystem clock operation mode must be performed from the x1 input clock operation mode. from subsystem clock operation mode, only x1 input clock operation mode can be shifted to. 5. do not set mcm0 = 0 (shifting to ring-osc) during subsystem clock operation. 6. do not set mstop = 1 during subsystem clock operation (even if mstop = 1 is set, x1 oscillation does not stop). to stop x1 oscillation duri ng subsystem clock operation, use mcc.
user?s manual u15947ej2v0ud 168 chapter 7 16-bit timer/even t counters 00 and 01 the ? ? ? ? ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 169 7.2 configuration of 16-bit timer/event counters 00 and 01 16-bit timer/event counters 00 and 01 consist of the following hardware. table 7-1. configuration of 16- bit timer/event counters 00 and 01 item configuration timer counter 16 bits (tm0n) register 16-bit timer capture/compar e register: 16 bits (cr00n, cr01n) timer input ti00n, ti01n timer output to0n, output controller control registers 16-bit timer mode control register 0n (tmc0n) 16-bit timer capture/compare control register 0n (crc0n) 16-bit timer output control register 0n (toc0n) prescaler mode register 0n (prm0n) port mode register 0 (pm0) port register 0 (p0) remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 170 figure 7-2. block diagram of 16-bit timer/event counter 01 (
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 171 (1) 16-bit timer counter 0n (tm0n) tm0n is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. figure 7-3. format of 16-bit timer counter 0n (tm0n) tm0n (n = 0, 1) symbol ff11h (tm00) ffb1h (tm01) ff10h (tm00) ffb0h (tm01) address: ff10h, ff11h (tm00), ffb0h, ffb1h (tm01) after reset: 0000h r the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc0n3 and tmc0n2 are cleared <3> if the valid edge of ti00n is input in the mode in wh ich clear & start occurs when inputting the valid edge of ti00n <4> if tm0n and cr00n match in the mode in which cl ear & start occurs on a match of tm0n and cr00n <5> ospt0n is set in one-shot pulse output mode (2) 16-bit timer capture/comp are register 00n (cr00n) cr00n is a 16-bit register that has the functions of both a capture register and a compar e register. whether it is used as a capture register or as a comp are register is set by bit 0 (crc0n0) of capture/compar e control register 0n (crc0n). cr00n can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. figure 7-4. format of 16-bit timer ca pture/compare register 00n (cr00n) cr00n (n = 0, 1) symbol ff13h (cr000) ffb3h (cr001) ff12h (cr000) ffb2h (cr001) address: ff12h, ff13h (cr000), ffb2h, ffb3h (cr001) after reset: 0000h r/w ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 172 table 7-2. cr00n capture trigger and valid edges of ti00n and ti01n pins (1) ti00n pin valid edge selected as captu re trigger (crc0n1 = 1, crc0n0 = 1) ti00n pin valid edge cr00n capture trigger es0n1 es0n0 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti01n pin valid edge selected as captu re trigger (crc0n1 = 0, crc0n0 = 1) ti01n pin valid edge cr00n capture trigger es1n1 es1n0 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es0n1, es0n0 = 1, 0 and es1n1, es1n0 = 1, 0 is prohibited. 2. es0n1, es0n0: bits 5 and 4 of prescaler mode register 0n (prm0n) es1n1, es1n0: bits 7 and 6 of prescaler mode register 0n (prm0n) crc0n1, crc0n0: bits 1 and 0 of capture/ compare control register 0n (crc0n) 3. n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 173 (3) 16-bit timer capture/comp are register 01n (cr01n) cr01n is a 16-bit register that has the functions of both a capture register and a compar e register. whether it is used as a capture register or a compare register is set by bit 2 (crc0n2) of capture/ compare control register 0n (crc0n). cr01n can be set by a 16-bit memory manipulation instruction. reset input clears this register to 0000h. figure 7-5. format of 16-bit timer ca pture/compare register 01n (cr01n) cr01n (n = 0, 1) symbol ff15h (cr010) ffb5h (cr011) ff14h (cr010) ffb4h (cr011) address: ff14h, ff15h (cr010), ffb4h, ffb5h (cr011) after reset: 0000h r/w ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 174 7.3 registers controlling 16-bit timer/event counters 00 and 01 the following six registers are used to cont rol 16-bit timer/event counters 00 and 01. ? ? ? ? ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 175 figure 7-6. format of 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 tmc001 <0> ovf00 symbol tmc00 address: ffbah after reset: 00h r/w ovf00 16-bit timer counter 00 (tm00) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf00 flag. 2. set the valid edge of the ti000/p00 pin using prescaler mode register 00 (prm00). 3. if any of the following mod es is selected: the mode in whic h clear & start occurs on match between tm00 and cr000, the mode in which clear & start occurs at the ti00 valid edge, or free-running mode, when the set value of cr000 is ffffh and the tm00 value changes from ffffh to 0000h, the ovf00 flag is set to 1. remarks 1. to00: 16-bit timer/event counter 00 output pin 2. ti000: 16-bit timer/event counter 00 input pin 3. tm00: 16-bit timer counter 00 4. cr000: 16-bit timer capture/compare register 000 5. cr010: 16-bit timer capture/compare register 010 tmc003 tmc002 tmc001 operating mode and clear mode selection to00 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 0 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 1 0 0 1 0 1 clear & start occurs on ti000 valid edge ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 176 figure 7-7. format of 16-bit timer mode control register 01 (tmc01) 7 0 6 0 5 0 4 0 3 tmc013 2 tmc012 1 tmc011 <0> ovf01 symbol tmc01 address: ffb6h after reset: 00h r/w ovf01 16-bit timer counter 01 (tm01) overflow detection 0 overflow not detected 1 overflow detected cautions 1. timer operation must be stopped before writing to bits other than the ovf01 flag. 2. set the valid edge of the ti001/p05 pin using prescaler mode register 01 (prm01). 3. if any of the following mod es is selected: the mode in whic h clear & start occurs on match between tm01 and cr001, the mode in which clear & start occurs at the ti01 valid edge, or free-running mode, when the set value of cr001 is ffffh and the tm01 value changes from ffffh to 0000h, the ovf01 flag is set to 1. remarks 1. to01: 16-bit timer/event counter 01 output pin 2. ti001: 16-bit timer/event counter 01 input pin 3. tm01: 16-bit timer counter 01 4. cr001: 16-bit timer capture/compare register 001 5. cr011: 16-bit timer capture/compare register 011 tmc013 tmc012 tmc011 operating mode and clear mode selection to01 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm01 cleared to 0) no change not generated 0 1 0 free-running mode match between tm01 and cr001 or match between tm01 and cr011 0 1 1 match between tm01 and cr001, match between tm01 and cr011 or ti001 valid edge 1 0 0 1 0 1 clear & start occurs on ti001 valid edge ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 177 (2) capture/compare control register 0n (crc0n) this register controls the oper ation of the 16-bit timer capture/ compare registers (cr00n, cr01n). crc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0n to 00h. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 178 figure 7-9. format of capture/comp are control register 01 (crc01) address: ffb8h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc01 0 0 0 0 0 crc012 crc011 crc010 crc012 cr011 operating mode selection 0 operates as compare register 1 operates as capture register crc011 cr001 capture trigger selection 0 captures on valid edge of ti011 1 captures on valid edge of ti001 by reverse phase crc010 cr001 operating mode selection 0 operates as compare register 1 operates as capture register cautions 1. timer operation must be stopped before setting crc01. 2. when the mode in which clear & start occurs on a match betw een tm01 and cr001 is selected with 16-bit timer mode control register 01 (tmc01), cr0 01 should not be specified as a capture register. 3. the capture operation is not performed if both the rising and falling edges ar e specified as the valid edge of ti001. 4. to ensure that the capture operation is pe rformed properly, the cap ture trigger requires a pulse two cycles longer than th e count clock selected by pr escaler mode register 01 (prm01). (3) 16-bit timer output control register 0n (toc0n) this register controls the operation of 16-bit timer/event counter 0n output controller. it sets/resets the timer output f/f (lv0n), enables/disables output inversio n and 16-bit timer/event counter 0n timer output, enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software. toc0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0n to 00h. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 179 figure 7-10. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe00 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc004 timer output f/f control using match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control using match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free-running mode and the mode in which clear & start occurs at the ti000 vali d edge. in the mode in which clear & start occurs on a match between the tm00 register and cr000 register, one-shot pulse output is not possi ble because an overflow does not occur. cautions 1. timer operation must be st opped before setting other than toc004. 2. if lvs00 and lvr00 are read, 0 is read. 3. ospt00 is automatically cleared after data is set, so 0 is read. 4. do not set ospt00 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 00 (prm00) is required to write to ospt00 successively. 6. do not set lvs00 to 1 before toe00, and do not set lvs00 and toe00 to 1 simultaneously.
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 180 figure 7-11. format of 16-bit timer ou tput control register 01 (toc01) address: ffb9h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc01 0 ospt01 ospe01 toc014 lvs01 lvr01 toc011 toe01 ospt01 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe01 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc014 timer output f/f control using match of cr011 and tm01 0 disables inversion operation 1 enables inversion operation lvs01 lvr01 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc011 timer output f/f control using match of cr001 and tm01 0 disables inversion operation 1 enables inversion operation toe01 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free-running mode and the mode in which clear & start occurs at the ti001 vali d edge. in the mode in which clear & start occurs on a match between the tm01 register and cr001 register, one-shot pulse output is not possi ble because an overflow does not occur. cautions 1. timer operation must be st opped before setting other than toc014. 2. if lvs01 and lvr01 are read, 0 is read. 3. ospt01 is automatically cleared after data is set, so 0 is read. 4. do not set ospt01 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 01 (prm01) is required to write to ospt01 successively. 6. do not set lvs01 to 1 before toe01, and do not set lvs01 and toe01 to 1 simultaneously.
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 181 (4) prescaler mode register 0n (prm0n) this register is used to set the 16-bit timer counter 0n (tm0n) count clock and ti00n and ti01n input valid edges. prm0n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears prm0n to 00h. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 182 figure 7-12. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 0 prm001 prm000 es101 es100 ti010 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection 0 0 f x (10 mhz) 0 1 f x /2 2 (2.5 mhz) 1 0 f x /2 8 (39.06 khz) 1 1 ti000 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f x ). cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 16-bit timer/ev ent counter 00 is not guaranteed. when an external clock is used and when the ring-osc clock is selected and supplied to the cpu, the operation of 16-bit timer/event counter 00 is not guaranteed, either, because the ring-osc clock is supplied as the samplin g clock to eliminate noise. 2. always set data to prm00 a fter stopping the timer operation. 3. if the valid edge of ti000 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti 000 and the capture trigger. 4. if the ti000 or ti010 pin is high level immediatel y after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to en able the operation of 16-bit timer counter 00 (tm00). care is therefore required when pulli ng up the ti000 or ti010 pin. however, when re- enabling operation after the operation has b een stopped once, the rising edge is not detected. 5. when p01 is used as the ti010 valid edge, it cannot be used as the timer output (to00), and when used as to00, it cannot be used as the ti010 valid edge. remarks 1 . f x : x1 input clock oscillation frequency 2. ti000, ti010: 16-bit timer/ event counter 00 input pin 3. figures in parentheses are for operation with f x = 10 mhz.
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 183 figure 7-13. format of prescaler mode register 01 (prm01) address: ffb7h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm01 es111 es110 es011 es010 0 0 prm011 prm010 es111 es110 ti011 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es011 es010 ti001 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm011 prm010 count clock selection 0 0 f x (10 mhz) 0 1 f x /2 4 (625 khz) 1 0 f x /2 6 (156.25 khz) 1 1 ti001 valid edge note note the external clock requires a pulse two cycles longer than internal clock (f x ). cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 16-bit timer/ev ent counter 01 is not guaranteed. when an external clock is used and when the ring-osc clock is selected and supplied to the cpu, the operation of 16-bit timer/event counter 01 is not guaranteed, either, because the ring-osc clock is supplied as the samplin g clock to eliminate noise. 2. always set data to prm01 a fter stopping the timer operation. 3. if the valid edge of ti001 is to be set for the count clock, do not set the clear & start mode using the valid edge of ti 001 and the capture trigger. 4. if the ti001 or ti011 pin is high level immediatel y after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti001 pin or ti011 pin to en able the operation of 16-bit timer counter 01 (tm01). care is therefore required when pulli ng up the ti001 or ti011 pin. however, when re- enabling operation after the operation has b een stopped once, the rising edge is not detected. 5. when p06 is used as the ti011 valid edge, it cannot be used as the timer output (to01), and when used as to01, it cannot be used as the ti011 valid edge. remarks 1 . f x : x1 input clock oscillation frequency 2. ti001, ti011: 16-bit timer/ event counter 01 input pin 3. figures in parentheses are for operation with f x = 10 mhz.
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 184 (5) port mode register 0 (pm0) this register sets port 0 input/output in 1-bit units. when using the p01/ to00/ti010 and p06/to01 note /ti011 note pins for timer output, clear pm01 and pm06 and the output latches of p01 and p06 to 0. when using the p01/to00/ti010 and p06/to01 note /ti011 note pins for timer input, clear pm01 and pm06 to 0. at this time, the output latches of p01 and p06 may be 0 or 1. pm0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0 to ffh. figure 7-14. format of port mode register 0 (pm0) 7 1 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 symbol pm0 address: ff20h after reset: ffh r/w pm0n 0 1 p0n pin i/o mode selection (n = 0 to 6) output mode (output buffer on) input mode (output buffer off) note available only for the
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 185 7.4 operation of 16-bit timer/ event counters 00 and 01 7.4.1 interval timer operation setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-15 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-15 for the set value). <2> set any value to the cr00n register. <3> set the count clock by using the prm0n register. <4> set the tmc0n register to start the operation (see figure 7-15 for the set value). caution cr00n cannot be rewr itten during tm0n operation. remark for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (cr00n) as the interval. when the count value of 16-bit timer counter 0n (tm0n) matches the value set in cr00n, counting continues with the tm0n value cleared to 0 and the interrupt request signal (inttm00n) is generated. the count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 186 figure 7-15. control register setti ngs for interval timer operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remarks 1. 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. 2. n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 187 figure 7-16. interval ti mer configuration diagram 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) ovf0n clear circuit inttm00n f x (f x ) note 1 f x /2 2 (f x /2 4 ) note 1 f x /2 8 (f x /2 6 ) note 1 ti000/p00 (ti001/p05) note 1 selector noise eliminator f x note 2 notes 1. frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. 2. ovf0n is set to 1 only when 16-bit timer capt ure/compare register 00n is set to ffffh. figure 7-17. timing of interval timer operation count clock t tm0n count value cr00n inttm00n 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt acknowledged interrupt acknowledged remark interval time = (n + 1)
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 188 7.4.2 ppg output operations setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-18 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-18 for the set value). <2> set any value to the cr00n register as the cycle. <3> set any value to the cr01n register as the duty factor. <4> set the toc0n register (see figure 7-18 for the set value). <5> set the count clock by using the prm0n register. <6> set the tmc0n register to start the operation (see figure 7-18 for the set value). caution to change the value of the duty factor (the value of the cr01n register) during operation, see caution 2 in figure 7-20 ppg output operation timing. remarks 1. for the setting of the to0n pin, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . in the ppg output oper ation, rectangular wa ves are output from the to0n pin with the pulse wi dth and the cycle that correspond to the count values preset in 16-bit time r capture/compare register 01n (cr01n) and in 16-bit timer capture/compare register 00n (cr00n), respectively. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 189 figure 7-18. control register settings for ppg output operation (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0 crc0n1
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 190 figure 7-19. configuration diagram of ppg output 16-bit timer capture/compare register 00n (cr00n) 16-bit timer counter 0n (tm0n) clear circuit noise eliminator f x f x (f x ) note f x /2 2 (f x /2 4 ) note f x /2 8 (f x /2 6 ) note ti000/p00 (ti001/p05) note 16-bit timer capture/compare register 01n (cr01n) to00/ti010/p01 ( to01/ti011/p06 ) selector output controller note frequencies and pin names without parentheses are for 16-bit timer/event counter 00, and those in parentheses are for 16-bit timer/event counter 01. figure 7-20. ppg output operation timing t 0000h 0000h 0001h 0001h m ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 191 7.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00n pin and ti01n pin using 16-bit timer counter 0n (tm0n). there are two measurement methods: measuring with tm0n used in free-running mode, and measuring by restarting the timer in synchronization with th e edge of the signal in put to the ti00n pin. when an interrupt occurs, read the valid value of the capt ure register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed unt il the signal pulse width is sampl ed in the count clock cycle selected by prescaler mode register 0n (prm0n) and the valid level of the ti00n or ti01n pin is dete cted twice, thus eliminating noise with a short pulse width. figure 7-21. cr01n capture operat ion with rising edge specified count clock tm0n ti00n rising edge detection cr01n inttm01n n ? ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 192 (1) pulse width measurement with free-runni ng counter and one capture register when 16-bit timer counter 0n (tm0n) is operated in free-ru nning mode, and the edge specified by prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit timer capture/compare register 01n (cr01n) and an external interrupt request signal (inttm01n) is set. specify both the rising and falling edges by usi ng bits 4 and 5 (es0n0 and es0n1) of prm0n. sampling is performed using the count clock selected by prm0n, and a capture operation is only performed when a valid level of the ti00n pin is detected twic e, thus eliminating noise with a short pulse width. figure 7-22. control register settings for pul se width measurement with free-running counter and one capture register (whe n ti00n and cr01n are used) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 1 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 193 figure 7-23. configuration di agram for pulse width measureme nt with free-running counter f x (f x ) note f x /2 2 (f x /2 4 ) note f x /2 8 (f x /2 6 ) note ti00n 16-bit timer counter 0n (tm0n) ovf0n 16-bit timer capture/compare register 01n (cr01n) internal bus inttm01n selector note frequencies without parentheses are for 16-bit timer/ev ent counter 00, and those in parentheses are for 16- bit timer/event counter 01. figure 7-24. timing of pulse width measureme nt operation with free-running counter and one capture register ( with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 count clock tm0n count value ti00n pin input cr01n capture value inttm01n ovf0n (d1 ? ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 194 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0n (tm0n) is operated in free- running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the ti00n pin and the ti01n pin. when the edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bit time r capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the edge specified by bits 6 and 7 (es1n0 and es1n1) of prm0n is input to the ti01n pin, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n) and an interrupt request signal (inttm00n) is set. specify both the rising and falling edges as the edges of the ti00n and ti01n pins, by using bits 4 and 5 (es0n0 and es0n1) and bits 6 and 7 (es1n0 and es1n1) of prm0n. sampling is performed using the co unt clock cycle selected by prescale r mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n or ti01n pin is detected twice, thus eliminating noise with a short pulse width. figure 7-25. control register settings for measure ment of two pulse widths with free-running counter (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 0 crc0n0 1 crc0n cr00n used as capture register captures valid edge of ti01n pin to cr00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 1 es1n0 1 es0n1 1 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 195 figure 7-26. timing of pulse width measure ment operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 ti01n pin input cr00n capture value inttm01n inttm00n ovf0n (d1 ? ? ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 196 (3) pulse width measurement with free-runni ng counter and two capture registers when 16-bit timer counter 0n (tm0n) is operated in free -running mode, it is possible to measure the pulse width of the signal input to the ti00n pin. when the rising or falling edge specified by bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n) is input to the ti00n pin, the value of tm0n is taken into 16-bi t timer capture/compare register 01n (cr01n) and an interrupt request signal (inttm01n) is set. also, when the inverse edge to that of the capture operation is input into cr 01n, the value of tm0n is taken into 16-bit timer capture/compare register 00n (cr00n). sampling is performed using the co unt clock cycle selected by prescale r mode register 0n (prm0n), and a capture operation is only performed when a valid level of the ti00n pin is detected twice, thus eliminating noise with a short pulse width. figure 7-27. control register settings for pulse width measurement with fr ee-running counter and two capture registers (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 0 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n free-running mode (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 1 crc0n0 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 197 figure 7-28. timing of pulse width measureme nt operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 inttm01n ovf0n d2 d1 d3 d2 d3 d0 + 1 d2 + 1 d1 d1 + 1 cr00n capture value count clock tm0n count value ti00n pin input cr01n capture value (d1 ? ? ? ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 198 figure 7-29. control register settings for pu lse width measurement by means of restart (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 0 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts at valid edge of ti00n pin. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 1 crc0n1 1 crc00n 1 crc0n cr00n used as capture register captures to cr00n at inverse edge to valid edge of ti00n. cr01n used as capture register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) figure 7-30. timing of pulse width measure ment operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm01n d1
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 199 7.4.4 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-31 for the set value). <2> set the count clock by using the prm0n register. <3> set any value to the cr00n register (0000h cannot be set). <4> set the tmc0n register to start the operation (see figure 7-31 for the set value). remarks 1. for the setting of the ti00n pin, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . the external event counter counts the num ber of external clock pulses input to the ti00n pin using 16-bit timer counter 0n (tm0n). tm0n is incremented each time the valid edge specified by prescaler mode register 0n (prm0n) is input. when the tm0n count value matches the 16-bit timer capt ure/compare register 00n (cr00n) value, tm0n is cleared to 0 and the interrupt requ est signal (inttm00n) is generated. input a value other than 0000h to cr00n (a count operation with 1-bit pulse cannot be carried out). any of three edges ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 200 figure 7-31. control register settings in external ev ent counter mode (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0/1 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register (c) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0 es0n0 1 3 0 2 0 prm0n1 1 prm0n0 1 prm0n selects external clock. specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respecti ve control registers for details. n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 201 figure 7-32. configuration diagra m of external event counter f x internal bus 16-bit timer capture/compare register 00n (cr00n) match clear ovf0n note noise eliminator 16-bit timer counter 0n (tm0n) valid edge of ti00n inttm00n note ovf0n is set to 1 only when cr00n is set to ffffh. figure 7-33. external event counter oper ation timing (with rising edge specified) ti00n pin input tm0n count value cr00n inttm00n 0000h 0001h 0002h 0003h 0004h 0005h n ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 202 7.4.5 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figure 7-34 for the set value). <3> set the toc0n register (see figure 7-34 for the set value). <4> set any value to the cr00n register (0000h cannot be set). <5> set the tmc0n register to start the operation (see figure 7-34 for the set value). caution cr00n cannot be rewr itten during tm0n operation. remarks 1. for the setting of the to0n pin, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n interrupt, see chapter 19 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16- bit timer capture/compare register 00n (cr00n). the to0n pin output status is reversed at intervals determined by the count value preset to cr00n + 1 by setting bit 0 (toe0n) and bit 1 (toc0n1) of 16-bit timer output control register 0n (toc0n) to 1. this enables a square wave with any selected frequency to be output. figure 7-34. control register settings in square-wave output mode (1/2) (a) 16-bit timer mode cont rol register 0n (tmc0n) 7 0 6 0 5 0 4 0 tmc0n3 1 tmc0n2 1 tmc0n1 0 ovf0n 0 tmc0n clears and starts on match between tm0n and cr00n. (b) capture/compare cont rol register 0n (crc0n) 7 0 6 0 5 0 4 0 3 0 crc0n2 0/1 crc0n1 0/1 crc0n0 0 crc0n cr00n used as compare register
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 203 figure 7-34. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 0n (toc0n) 7 0 ospt0n 0 ospe0n 0 toc0n4 0 lvs0n 0/1 lvr0n 0/1 toc0n1 1 toe0n 1 toc0n enables to0n output. inverts output on match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited). does not invert output on match between tm0n and cr01n. disables one-shot pulse output. (d) prescaler mode register 0n (prm0n) es1n1 0/1 es1n0 0/1 es0n1 0/1 es0n0 0/1 3 0 2 0 prm0n1 0/1 prm0n0 0/1 prm0n selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. n = 0: ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 204 7.4.6 one-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti00n pin input). setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm0n register. <2> set the crc0n register (see figures 7-36 and 7-38 for the set value). <3> set the toc0n register (see figures 7-36 and 7-38 for the set value). <4> set any value to the cr00n and cr01n registers (0000h cannot be set). <5> set the tmc0n register to start the operation (see figures 7-36 and 7-38 for the set value). remarks 1. for the setting of the to0n pin, see 7.3 (5) port mode register 0 (pm0) . 2. for how to enable the inttm00n (if necessary, inttm01n) interrupt, see chapter 19 interrupt functions . (1) one-shot pulse output with software trigger a one-shot pulse can be output from t he to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 7-36, and by setting bit 6 (ospt0n) of the toc0n register to 1 by software. by setting the ospt0n bit to 1, 16-bit timer/event co unter 0n is cleared and starte d, and its output becomes active at the count value (n) set in advance to 16-bit time r capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 00n (cr00n) note . even after the one-shot pulse has been output, the tm0n regi ster continues its operat ion. to stop the tm0n register, the tmc0n3 and tmc0n2 bits of the tmc0n register must be cleared to 00. note the case where n < m is described here. w hen n > m, the output becom es active with the cr00n register and inactive with the cr01n register. do not set n to m. cautions 1. do not set the ospt0n bit while the one-shot pulse is being outpu t. to output the one-shot pulse again, wait until the current one-s hot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the ti 00n pin or its alternate-function port pin. because the external trigger is valid even in this case, the ti mer is cleared and started even at the level of the ti00n pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 205 figure 7-36. control register settings for on e-shot pulse output with software trigger (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000 7654 0 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running mode 100 (b) capture/compare cont rol register 0n (crc0n) 00000 76543 crc0n crc0n2 crc0n1 crc0n0 cr00n as compare register cr01n as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 7 0 1 1 0/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output. inverts output upon match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited.) inverts output upon match between tm0n and cr01n. sets one-shot pulse output mode. set to 1 for output. 0/1 1 1 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0/1 0/1 0 prm0n prm0n1 prm0n0 selects count clock. setting invalid (setting ?10? is prohibited.) 0 0/1 0/1 es1n1 es1n0 es0n1 es0n0 setting invalid (setting ?10? is prohibited.) 32 caution do not set 0000h to the cr00n and cr01n registers. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 206 figure 7-37. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1 m ? 1 0001h m + 1 m + 2 0000h count clock tm0n count cr01n set value cr00n set value ospt0n inttm01n inttm00n to0n pin output set tmc0n to 0ch (tm0n count starts) caution 16-bit timer counter 0n st arts operating as soon as a value othe r than 00 (operation stop mode) is set to the tmc0n3 and tmc0n2 bits. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from t he to0n pin by setting 16-bit timer mode control register 0n (tmc0n), capture/compare control register 0n (crc0n), and 16-bit timer output control register 0n (toc0n) as shown in figure 7-38, and by using the valid edge of the ti00n pin as an external trigger. the valid edge of the ti00n pin is specified by bits 4 and 5 (es0n0, es0n1) of prescaler mode register 0n (prm0n). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti00n pin is detected, the 16-bit time r/event counter is clear ed and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 01n (cr01n). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 00n (cr00n) note . note the case where n < m is described here. w hen n > m, the output becom es active with the cr00n register and inactive with the cr01n register. do not set n to m. caution even if the external trigger is generated again while the one-shot pulse is output, it is ignored. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 207 figure 7-38. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (a) 16-bit timer mode cont rol register 0n (tmc0n) 0000 7654 1 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti00n pin. 000 (b) capture/compare cont rol register 0n (crc0n) 00000 76543 crc0n crc0n2 crc0n1 crc0n0 cr00n used as compare register cr01n used as compare register 0 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 0 7 01 1 0/1 toc0n lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n enables to0n output. inverts output upon match between tm0n and cr00n. specifies initial value of to0n output f/f (setting ?11? is prohibited.) inverts output upon match between tm0n and cr01n. sets one-shot pulse output mode. 0/1 1 1 (d) prescaler mode register 0n (prm0n) 0/1 0/1 0 1 prm0n prm0n1 prm0n0 selects count clock (setting ?11? is prohibited). specifies the rising edge for pulse width detection. 0/1 0/1 es1n1 es1n0 es0n1 es0n0 setting invalid (setting ?10? is prohibited.) 00 32 caution do not set 0000h to the cr00n and cr01n registers. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 208 figure 7-39. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? ?
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 209 7.5 cautions for 16-bit timer/event counters 00 and 01 (1) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 16-bit timer counter 0n (tm0n) is started asynchronously to the count clock. figure 7-40. start timing of 16-bit timer counter 0n (tm0n) tm0n count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture/compare re gister setting (in the mode in wh ich clear & start occurs on match between tm0n and cr00n) set 16-bit timer capture/compare registers 00n and 01n (cr 00n and cr01n) to other than 0000h. this means a 1-pulse count operation cannot be performed when 16-bit timer/event counter 0n is used as an event counter. (3) capture register data retention timing the values of 16-bit timer capture/ compare registers 00n and 01n (cr00n and cr01n) are not guaranteed after 16-bit timer/event counter 0n has been stopped. (4) valid edge setting set the valid edge of the ti00n pin after clearing bits 2 and 3 (tmc0n2 and tmc0n3) of 16-bit timer mode control register 0n (tmc0n) to 0, 0, respectively, and then sto pping timer operation. the valid edge is set using bits 4 and 5 (es0n0 and es0n1) of prescaler mode register 0n (prm0n). (5) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set the ospt0n bit to 1. do not output the one-shot pulse again until inttm00n, which occurs upon a match with the cr00n register, or inttm01n, which occurs upon a match with the cr01n register, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output of 16-bit timer/ev ent counter 0n with a software trigger, do not change the level of the ti00n pin or its alternate function port pin. because the external trigger is valid even in this case, the timer is cleared and started even at the level of the ti00n pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. remark n = 0:
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 210 (6) operation of ovf0n flag <1> the ovf0n flag is also set to 1 in the following case. when any of the follo wing modes is selected: the mode in whic h clear & start occurs on a match between tm0n and cr00n, the mode in which clear & start occurs at the ti0n valid edge, or the free-running mode
chapter 7 16-bit timer/event counters 00 and 01 user?s manual u15947ej2v0ud 211 (8) timer operation <1> even if 16-bit timer counter 0n (tm0n) is read, t he value is not captured by 16-bit timer capture/compare register 01n (cr01n). <2> regardless of the cpu?s operation mode, when the timer stops, the input signals to the ti00n/ti01n pins are not acknowledged. <3> the one-shot pulse output mode oper ates correctly only in the free-ru nning mode and the mode in which clear & start occurs at the ti00n vali d edge. in the mode in which clear & start occurs on a match between the tm0n register and cr00n register, one-shot pulse output is not possi ble because an overflow does not occur. (9) capture operation <1> if ti00n valid edge is specified as the count clock, a capture operation by the capt ure register specified as the trigger for ti00n is not possible. <2> to ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 0n (prm0n). <3> the capture operation is performed at the falling edge of the count clock. an interrupt request input (inttm00n/inttm01n), however, is generated at the rise of the next count clock. (10) compare operation a capture operation may not be performed for cr00n/cr01n se t in compare mode even if a capture trigger has been input. (11) edge detection <1> if the ti00n or ti01n pin is high level immediately a fter system reset and the rising edge or both the rising and falling edges are specified as the valid edge of the ti 00n or ti01n pin to enable the 16-bit timer counter 0n (tm0n) operation, a rising ed ge is detected immediately after the operation is enabled. be careful therefore when pulling up the ti00n or ti 01n pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to remove noise differs w hen the ti00n valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x , and in the latter case the count clock is selected by prescaler mode register 0n (prm0n). the capture operation is only performed when a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width. remark n = 0:
user?s manual u15947ej2v0ud 212 chapter 8 8-bit timer/even t counters 50 and 51 8.1 functions of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 213 figure 8-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/p33/intp4 f x /2 8 f x /2 12 f x f x /2 match mask circuit ovf clear 3 selector tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/ p33/intp4 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector output latch (p33) pm33 f x /2 6 f x /2 4 notes 1. timer output f/f 2. pwm output f/f
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 214 8.2 configuration of 8-bit timer/event counters 50 and 51 8-bit timer/event counters 50 and 51 c onsist of the following hardware. table 8-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 1 (pm1) or port mode register 3 (pm3) port register 1 (p1) or port register 3 (p3) (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 8-3. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0, 1) address: ff16h (tm50), ff1fh (tm51) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which clear & start occurs upon a match of the tm5n and cr5n.
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 215 (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in pwm mode, when the to5n pin becomes active due to a tm5n overflow and the values of tm5n and cr5n match, the to5n pin becomes inactive. the value of cr5n can be set within 00h to ffh. reset input clears cr5n to 00h. figure 8-4. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0, 1) address: ff17h (cr50), ff41h (cr51) after reset: 00h r/w cautions 1. in the mode in which clear & start oc curs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite peri od 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 216 8.3 registers controlling 8-bi t timer/event counters 50 and 51 the following four registers are used to co ntrol 8-bit timer/event counters 50 and 51. ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 217 figure 8-6. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection 0 0 0 ti51 falling edge 0 0 1 ti51 rising edge 0 1 0 f x (10 mhz) 0 1 1 f x /2 (5 mhz) 1 0 0 f x /2 4 (625 khz) 1 0 1 f x /2 6 (156.25 khz) 1 1 0 f x /2 8 (39.06 khz) 1 1 1 f x /2 12 (2.44 khz) cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit ti mer/event counter 51 is not guaranteed. 2. when rewriting tcl51 to other da ta, stop the timer operation beforehand. 3. be sure to clea r bits 3 to 7 to 0. remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz.
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 218 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> timer output f/f (flip-flop) status setting <4> active level selection in timer f/f control or pwm (free-running) mode <5> timer output control tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0, 1 figure 8-7. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (tm50 output is low level) 1 output enabled (refer to the next page for caution and remark .)
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 219 figure 8-8. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (tm51 output is low level) 1 output enabled cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. do not rewrite following bits simultaneously. ? ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 220 (3) port mode registers 1 and 3 (pm1, pm3) these registers set port 1 and 3 input/output in 1-bit units. when using the p17/to50/ti50 and p33/ to51/ti51 pins for timer output, clear pm17 and pm33 and the output latches of p17 and p33 to 0. when using the p17/to50/ti50 and p33/ to51/ti51 pins for timer input, set pm17 and pm33 to 1. the output latches of p17 and p33 at this time may be 0 or 1. pm1 and pm3 can be set by a 1-bit or 8- bit memory manipulation instruction. reset input sets these registers to ffh. figure 8-9. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 8-10. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 0 0 0 0 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 221 8.4 operations of 8-bit timer/event counters 50 and 51 8.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval timer t hat generates interrupt reques ts repeatedly at intervals of the count value preset to 8-bi t timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 222 figure 8-11. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01 fe ff 00 fe ff 00 ff ff ff interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 223 8.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to ti5n by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection regist er 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit ti mer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 224 8.4.3 square-wave output operation a square wave with any selected frequency is output at in tervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n ) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 225 figure 8-13. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output c an be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 8.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 226 (1) pwm output basic operation setting <1> set each register. ? ? ? ? ? ? ?
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 227 figure 8-14. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> <3> inactive level active level <5> t (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n to5n inactive level inactive level 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h n + 2 l t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h ffh n + 2 inactive level active level inactive level active level inactive level t remarks 1. <1> to <3> and <5> in figure 8-14 (a) correspond to <1> to <3> and <5> in pwm output operation in 8.4.4 (1) pwm output basic operation . 2. n = 0, 1
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 228 (2) operation with cr5n changed figure 8-15. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh
chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15947ej2v0ud 229 8.5 cautions for 8-bit timer/event counters 50 and 51 (1) timer start error an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 8-bit timer counters 50 and 51 (tm50, tm 51) are started asynchronous ly to the count clock. figure 8-16. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0, 1
user?s manual u15947ej2v0ud 230 chapter 9 8-bit timers h0 and h1 9.1 functions of 8-bit timers h0 and h1 8-bit timers h0 and h1 have the following functions. ? ? ? ?
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 231 figure 9-1. block diag ram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 toh0/p15 inttmh0 f x f x /2 f x /2 2 f x /2 6 f x /2 10 1 0 f/f r 3 2 pm15 match internal bus 8-bit timer h mode control register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) output latch (p15) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 232 figure 9-2. block diag ram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/ intp5/ p16 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 selector f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 interrupt generator output controller level inversion pm16 output latch (p16) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode control register 1 (tmhmd1) selector
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 233 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-3. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0, 1) address: ff18h (cmp00), ff1ah (cmp01) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritte n during timer count operation. (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-4. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0, 1) address: ff19h (cmp10), ff1bh (cmp11) after reset: 00h r/w 7 6 5 4 32 1 0 cmp1n can be rewritten during timer count operation. an interrupt request signal (inttmhn) is generated if the values of the timer counter and cmp1n match after setting cmp1n in carrier generator mode. the timer counter va lue is cleared at the same time. if the cmp1n value is rewritten during timer operation, transferring is performed at the timing at which the counter value and cmp1n value match. if the transfer timing and writing from cpu to cmp1n conflict, transfer is not performed. caution in the pwm output mode and carrier genera tor mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the ti mer count operation was stopped (tmhen = 0) (be sure to set again even if se tting the same value to cmp1n). remark n = 0, 1
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 234 9.3 registers controlling 8-bit timers h0 and h1 the following four registers are used to control 8-bit timers h0 and h1. ? ? ? ?
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 235 figure 9-5. format of 8-bit time r h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w f x f x /2 f x /2 2 f x /2 6 f x /2 10 tm50 output note cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 (10 mhz) (5 mhz) (2.5 mhz) (156.25 khz) (9.77 khz) count clock (f cnt ) selection setting prohibited other than above interval timer mode pwm output mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> note to select the tm50 output as a count clock, start operation by setting 8-bit timer/event counter 50 in the pwm output mode (bit 6 (tmc506) of the tmc50 regist er = 1), and then set cks02, cks01, and cks00 to 1, 0, and 1, respectively. set the high/low level width of the count clock so that the specifications of the input width of ti50 are satisfied (see ac characteristics (1) basic operation in chapter 30 to chapter 32 ). it is not necessary to enable the to50 pin as a timer output pin (bit 0 (toe50) of the tmc register may be 0 or 1).
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 236 cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit timer h0 is not guaranteed. 2. when tmhe0 = 1, setting the other bits of the tmhmd0 register is prohibited. 3. in the pwm output mode, be sure to set 8- bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same val ue to the cmp10 register). remarks 1. f x : x1 input clock oscillation frequency 2. figures in parentheses apply to operation at f x = 10 mhz
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 237 figure 9-6. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w f x f x /2 2 f x /2 4 f x /2 6 f x /2 12 f r /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz (typ.)) count clock (f cnt ) selection setting prohibited other than above interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 tmmd10 0 1 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> cautions 1. when the ring-osc clo ck is selected as the clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as th e count clock. if the count clock is the ring-osc clock, the operation of 8-bit timer h1 is not guaranteed (except when cks12, cks11, cks10 = 1, 0, 1 (f r /2 7 )). 2. when tmhe1 = 1, setting the other bits of the tmhmd1 register is prohibited. 3. in the pwm output mode and carrier genera tor mode, be sure to set 8-bit timer h compare register 11 (cmp11) when star ting the timer count operation (tmh e1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 4. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51.
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 238 remarks 1. f x : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency 3. figures in parentheses apply to operation at f x = 10 mhz, f r = 240 khz (typ.). (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 9-7. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note low-level output high-level output low-level output carrier pulse output rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p15/toh0 and p16/toh1/intp5 pins for timer output, clear pm15 and pm16 and the output latches of p15 and p16 to 0. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 9-8. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 239 9.4 operation of 8-bit timers h0 and h1 9.4.1 operation as interval timer/square-wave output when 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of 8-bit timer counter hn and the cmp1n register is not detected even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. (1) usage generates the inttmhn signal repeatedly at the same interval. <1> set each register. figure 9-9. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting ?
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 240 (2) timing chart the timing of the interval timer/square- wave output operation is shown below. figure 9-10. timing of interval time r/square-wave output operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer counter hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, the tohn output level is in verted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive by clearing the tmhen bit to 0 during timer hn operation. if these are inactive from the first, the level is retained. remark n = 0, 1 n = 01h to feh
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 241 figure 9-10. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0, 1
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 242 9.4.2 operation as pwm output mode in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (cmp0n ) controls the cycle of timer output (t ohn). rewriting the cmp0n register during timer operation is prohibited. 8-bit timer compare register 1n (cmp1n) controls the dut y of timer output (tohn). re writing the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. tohn output becomes active and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. tohn output becomes inactive when 8-bit timer counter hn and the cmp1n register match. (1) usage in pwm output mode, a pulse for which an arbitr ary duty and arbitrary cycle can be set is output. <1> set each register. figure 9-11. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled timer output level inversion setting pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0, 1 2. 00h cmp1n (m) < cmp0n (n) ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare register that is to be compared first after counter operation is enabled. when the values of 8-bit timer counter hn and the cmp0 n register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, a nd tohn output becomes active. at the same time, the compare register to be compared with 8-bit timer c ounter hn is changed from the cmp0n register to the cmp1n register.
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 243 <4> when 8-bit timer counter hn and the cmp1n regist er match, tohn output bec omes inactive and the compare register to be compared with 8-bit timer coun ter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n register is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n+1)/f cnt duty = active width : total widt h of pwm = (m + 1) : (n + 1) cautions 1. in pwm output mode , three operation clocks (signal sel ected using the cksn2 to cksn0 bits of the tmhmdn register) are required to transfer the cmp1n register value after rewriting the register. 2. be sure to set the cmp1n register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register).
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 244 (2) timing chart the operation timing in pwm output mode is shown below. caution make sure that the cmp1n register setting value (m) and cmp0 n register setting value (n) are within the following range. 00h
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 245 figure 9-12. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0, 1
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 246 figure 9-12. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0, 1
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 247 figure 9-12. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 01h
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 248 9.4.3 carrier generato r mode operation (8-bit timer h1 only) the carrier clock generated by 8-bit timer h1 is output in the cycle set by 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is out put from the toh1 output. (1) carrier generation in carrier generator mode, 8-bit timer h compare regist er 01 (cmp01) generates a low-level width carrier pulse waveform and 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during 8-bit timer h1 operat ion is possible but rewriting the cmp01 register is prohibited. (2) carrier output control carrier output is controlled by the interrupt request sig nal (inttm51) of 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier co ntrol register (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output 1 0 low-level output 1 1 carrier pulse output
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 249 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuratio n. the nrz1 bit is read-only but t he nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrzb1 bit to the nrz1 bit is as shown below. figure 9-13. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <1> the inttm51 signal is synchronized with the count cl ock of 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is transferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. cautions 1. do not rewrite the nrzb1 bit again until at least the second clock afte r it has been rewritten, or else the transfer from the nrzb1 bi t to the nrz1 bit is not guaranteed. 2. when 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs.
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 250 (3) usage outputs an arbitrary carrier clock from the toh1 pin. <1> set each register. figure 9-14. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled timer output level inversion setting carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 0/1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? ? ? ? ?
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 251 if the setting value of the cmp01 register is n, the setting value of the cmp 11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty = high-level width : carrier clock ou tput width = ( m + 1) : (n + m + 2) cautions 1. be sure to set the cm p11 register when starting the time r count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set agai n even if setting the same value to the cmp11 register). 2. set so that the count cloc k frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. (4) timing chart the carrier output control timing is shown below. cautions 1. set the values of the cmp01 and cmp11 registers in a range of 01h to ffh. 2. in the carrier generator mode, three ope rating clocks (signal selected by cks12 to cks10 bits of tmhmd1 register) or more are requi red from when the cmp11 register value is changed to when the value is transferred to the register. 3. be sure to set the rmc1 bit be fore the count operation is started.
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 252 figure 9-15. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n cmpn0 cmpn1 tmhen inttmhn carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l inttm5hn <1> <2> <3> <4> <5> <6> <7> 8-bit timer hn count clock 8-bit timer counter hn count value <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a c ount operation. at that time, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer sign al for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level.
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 253 figure 9-15. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n l cmpn0 cmpn1 tmhen inttmhn carrier clock tm5n count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l inttm5hn <1> <2> <3> <4> <5> <6> <7> 8-bit timer 5n count clock 8-bit timer hn count clock 8-bit timer counter hn count value <1> when tmhe1 = 0 and tce51 = 0, 8-bit timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, 8-bit timer counter h1 starts a c ount operation. at that time, the carrier clock is held at the inactive level. <3> when the count value of 8-bit timer counter h1 matc hes the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter h1 is switched from the cmp01 register to the cmp11 register. 8-bit timer counter h1 is cleared to 00h. <4> when the count value of 8-bit timer counter h1 matc hes the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and t he compare register to be compared with 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with 8-bit timer h1 count clock and output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
chapter 9 8-bit timers h0 and h1 user?s manual u15947ej2v0ud 254 figure 9-15. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, 8-bit timer h1 starts a count oper ation. at that time, the carrier clock is held at the inactive level. <2> when the count value of 8-bit timer counter h1 matche s the cmp01 register value, 8-bit timer counter h1 is cleared and the inttmh1 signal is output. <3> the cmp11 register can be rewritten during 8-bit timer h1 operation, however, the changed value (l) is latched. the cmp11 register is changed when the co unt value of 8-bit timer counter h1 and the cmp11 register value before t he change (m) match (<3>?). <4> when the count value of 8-bit timer counter h1 and the cmp11 register value before the change (m) match, the inttmh1 signal is output, the carrier signal is inve rted, and 8-bit timer counter h1 is cleared to 00h. <5> the timing at which the count value of 8-bit timer counter h1 and the cmp11 register value match again is indicated by the value after the change (l).
user?s manual u15947ej2v0ud 255 chapter 10 watch timer 10.1 functions of watch timer the watch timer has the following functions. ? ?
chapter 10 watch timer user?s manual u15947ej2v0ud 256 (1) watch timer when the x1 input clock or subsystem clock is used, interrupt reques ts (intwt) are gener ated at preset intervals. table 10-1. watch timer interrupt time interrupt time when operated at f xt = 32.768 khz when operated at f x = 10 mhz 2 4 /f w 488
chapter 10 watch timer user?s manual u15947ej2v0ud 257 10.2 configuration of watch timer the watch timer consists of the following hardware. table 10-3. watch timer configuration item configuration counter 5 bits ?
chapter 10 watch timer user?s manual u15947ej2v0ud 258 figure 10-2. format of watch timer operation mode register (wtm) address: ff6fh after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> wtm wtm7 wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm7 watch timer count clock selection 0 f x /2 7 (78.125 khz) 1 f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0 0 0 2 4 /f w 0 0 1 2 5 /f w 0 1 0 2 6 /f w 0 1 1 2 7 /f w 1 0 0 2 8 /f w 1 0 1 2 9 /f w 1 1 0 2 10 /f w 1 1 1 2 11 /f w wtm3 wtm2 interrupt time selection 0 0 2 14 /f w 0 1 2 13 /f w 1 0 2 5 /f w 1 1 2 4 /f w wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stop (clear both prescaler and timer) 1 operation enable caution do not change the count clock and interval ti me (by setting bits 4 to 7 (wtm4 to wtm7) of wtm) during watch timer operation. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : x1 input clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. figures in parentheses apply to operation with f x = 10 mhz, f xt = 32.768 khz.
chapter 10 watch timer user?s manual u15947ej2v0ud 259 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt r equest (intwt) at a specific time interval by using the x1 input clock or subsystem clock. when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer oper ation mode register (wtm) are set to 1, the count operation starts. when these bits are cleared to 0, t he 5-bit counter is cleared an d the count operation stops. when the interval timer is simultaneously operated, zero-s econd start can be achieved only for the watch timer by clearing wtm1 to 0. in this case, however, the 11-bit prescaler is not cleared. therefore, an error up to 2 11
chapter 10 watch timer user?s manual u15947ej2v0ud 260 10.4.2 interval timer operation the watch timer operates as interval timer which generates in terrupt requests (intwti) r epeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm 4 to wtm6) of the watch timer operation mode register (wtm). when bit 0 (wtm0) of the wtm is set to 1, the count oper ation starts. when this bit is cleared to 0, the count operation stops. table 10-5. interval timer interval time wtm6 wtm5 wtm4 interval time when operated at f xt = 32.768 khz (wtm7 = 1) when operated at f x = 10 mhz (wtm7 = 0) 0 0 0 2 4 /f w 488
chapter 10 watch timer user?s manual u15947ej2v0ud 261 10.5 cautions for watch timer when operation of the watch timer and 5- bit counter is enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the inte rval until the first interr upt request (intwt) is generated after the register is set does not exactly match the specif ication made with bit 3 (wtm3) of wtm. this is because there is a delay of one 11-bit prescaler output cycle until th e 5-bit counter starts counting. subsequently, however, the intwt signal is generated at the specified intervals. figure 10-4. example of generation of watch timer interrupt request (int wt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt
user?s manual u15947ej2v0ud 262 chapter 11 watchdog timer 11.1 functions of watchdog timer the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 22 reset function . table 11-1. loop detection time of watchdog timer loop detection time during ring-osc clock o peration during x1 input clock operation f r /2 11 (8.53 ms) f xp /2 13 (819.2
chapter 11 watchdog timer user?s manual u15947ej2v0ud 263 table 11-2. mask option setting an d watchdog timer operation mode mask option ring-osc cannot be stopped ring-osc can be stopped by software watchdog timer clock source fixed to f r note 1 . ? ? ? ? ? ? ?
chapter 11 watchdog timer user?s manual u15947ej2v0ud 264 11.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 11-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) figure 11-1. block diag ram of watchdog timer f r /2 2 clock input controller output controller internal reset signal wdcs2 internal bus wdcs1 wdcs0 f xp /2 4 wdcs3 wdcs4 01 1 selector 16-bit counter or f xp /2 13 to f xp /2 20 f r /2 11 to f r /2 18 watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 3 2 clear mask option (to set ?ring-osc cannot be stopped? or ?ring-osc can be stopped by software?)
chapter 11 watchdog timer user?s manual u15947ej2v0ud 265 11.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? ?
chapter 11 watchdog timer user?s manual u15947ej2v0ud 266 cautions 1. if data is written to wdtm, a wait cycle is generate d. do not write data to wdtm when the cpu is operating on the subsyst em clock and the x1 input clock is stopped. for details, see chap ter 35 cautions for wait. 2. set bits 7, 6, and 5 to 0, 1, and 1, respectively (when ?ring-osc cannot be stopped? is selected by a mask option, other values are ignored). 3. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing atte mpted a second time, an internal reset signal is generated. 4. wdtm cannot be set by a 1-bi t memory manipulation instruction. remarks 1. f r : ring-osc clock oscillation frequency 2. f xp : x1 input clock oscillation frequency 3.
chapter 11 watchdog timer user?s manual u15947ej2v0ud 267 11.4 operation of watchdog timer 11.4.1 watchdog timer operation when ?ring-osc ca nnot be stopped? is selected by mask option the operation clock of watchdog timer is fixed to the ring-osc. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1) . the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? ? ? ?
chapter 11 watchdog timer user?s manual u15947ej2v0ud 268 11.4.2 watchdog timer operation when ?ring-osc can be stopped by soft ware? is selected by mask option the operation clock of the watchdog timer can be selected as either the ring-osc clock or the x1 input clock. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1). the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? ? ? ? ? ? ? ?
chapter 11 watchdog timer user?s manual u15947ej2v0ud 269 11.4.3 watchdog timer operation in stop mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during stop instruction execution regardless of whether the x1 input clock or ring-osc clock is being used. (1) when the cpu clock and the watchdog time r operation clock are the x1 input clock (f xp ) when the stop instruction is executed when stop instruction is executed, o peration of the watchdog timer is stopp ed. after stop mode is released, counting stops for the oscillation stabiliz ation time set by the oscillation stab ilization time select register (osts) and then counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 11-4. operation in stop mode (cpu cl ock and wdt operation clock: x1 input clock) watchdog timer operating operation stopped operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) (2) when the cpu clock is the x1 input clock (f xp ) and the watchdog timer operati on clock is the ring-osc clock (f r ) when the stop instruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again usi ng the operation clock before the operati on was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 11-5. operation in stop mode (cpu clock: x1 input clock, wdt operation clock: ring-osc clock) watchdog timer operating f r f xp cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (set by osts register) operating operation stopped
chapter 11 watchdog timer user?s manual u15947ej2v0ud 270 (3) when the cpu clock is the ring-osc clock (f r ) and the watchdog timer operati on clock is the x1 input clock (f xp ) when the stop inst ruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is stopped until the timing of <1> or <2>, whichever is earlier , and then counting is started using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. <1> the oscillation stabilization time set by the oscillat ion stabilization time select register (osts) elapses. <2> the cpu clock is switched to the x1 input clock (f xp ). figure 11-6. operation in stop mode (cpu clock: ring-osc clock, wdt op eration clock: x1 input clock) <1> timing when counting is started afte r the oscillation stabilization time set by the oscillation stabilization time select register (osts) has elapsed watchdog timer operating operation stopped operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) <2> timing when counting is started after the cp u clock is switched to the x1 input clock (f xp ) operating operation stopped operating f r f xp f r
chapter 11 watchdog timer user?s manual u15947ej2v0ud 271 (4) when cpu clock and watchdog timer ope ration clock are the ring-osc clocks (f r ) during stop instruction execution when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, counting is started again usi ng the operation clock before the operati on was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 11-7. operation in stop mode (cpu clo ck and wdt operation clo ck: ring-osc clock) watchdog timer operating f r f xp cpu operation 17 clocks normal operation (ring-osc clock) clock supply stopped normal operation (ring-osc clock) oscillation stopped stop oscillation stabilization time (set by osts register) operating operation stopped 11.4.4 watchdog timer operation in ha lt mode (when ?ring-osc can be stopped by software? is selected by mask option) the watchdog timer stops counting during halt instruction execution regardle ss of whether the cpu clock is the x1 input clock (f xp ), ring-osc clock (f r ), or subsystem clock (f xt ), or whether the operation clock of the watchdog timer is the x1 input clock (f xp ) or ring-osc clock (f r ). after halt mode is released, counting is started again using the operation clock before the operation was st opped. at this time, the counter is not cleared to 0 but holds its value. figure 11-8. operation in halt mode watchdog timer operating f r f xp cpu operation normal operation operating halt operation stopped f xt normal operation
user?s manual u15947ej2v0ud 272 chapter 12 clock output/buzzer output controller 12.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsis. the clock selected with the clock output selection register (cks) is output. in addition, the buzzer output is intended for square- wave output of buzzer frequency selected with cks. figure 12-1 shows the block diagram of clock output/buzzer output controller. figure 12-1. block diagram of clo ck output/buzzer output controller f x f x /2 10 to f x /2 13 f x to f x /2 7 f xt bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/intp6/p140 buz/busy0/ intp7/p141 bcs0, bcs1 clock controller prescaler internal bus ccs3 clock output selection register (cks) ccs2 ccs1 ccs0 output latch (p141) pm141 output latch (p140) pm140 selector selector
chapter 12 clock output/buzzer output controller user?s manual u15947ej2v0ud 273 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller consists of the following hardware. table 12-1. clock output/buzzer output controller configuration item configuration control registers clock output selection register (cks) port mode register 14 (pm14) port register 14 (p14) 12.3 register controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? ?
chapter 12 clock output/buzzer output controller user?s manual u15947ej2v0ud 274 figure 12-2. format of clock out put selection register (cks) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3 2 1 0 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circui t operation stopped. buz fixed to low level. 1 clock division ci rcuit operation enabled. buz output enabled. bcs1 bcs0 buz output clock selection 0 0 f x /2 10 (9.77 khz) 0 1 f x /2 11 (4.88 khz) 1 0 f x /2 12 (2.44 khz) 1 1 f x /2 13 (1.22 khz) cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection 0 0 0 0 f x (10 mhz) 0 0 0 1 f x /2 (5 mhz) 0 0 1 0 f x /2 2 (2.5 mhz) 0 0 1 1 f x /2 3 (1.25 mhz) 0 1 0 0 f x /2 4 (625 khz) 0 1 0 1 f x /2 5 (312.5 khz) 0 1 1 0 f x /2 6 (156.25 khz) 0 1 1 1 f x /2 7 (78.125 khz) 1 0 0 0 f xt (32.768 khz) other than above setting prohibited remarks 1. f x : x1 input clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f x = 10 mhz or f xt = 32.768 khz.
chapter 12 clock output/buzzer output controller user?s manual u15947ej2v0ud 275 (2) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using the p140/intp6/pcl pin for clock output and the p141/busy0/intp7/buz pin for buzzer output, clear pm140, pm141 and the output latch of p140, p141 to 0. pm14 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm14 to ffh. figure 12-3. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 pm145 pm144 pm143 pm142 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 12 clock output/buzzer output controller user?s manual u15947ej2v0ud 276 12.4 clock output/buzzer output controller operations 12.4.1 clock output operation the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. as show n in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing high level of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (bcs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output.
user?s manual u15947ej2v0ud 277 chapter 13 a/d converter 13.1 functions of a/d converter the a/d converter converts an analog input signal into a digi tal value, and consists of up to eight channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following two functions. (1) 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani7. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. (2) power-fail de tection function this function is used to detect a voltage drop in a batte ry. the a/d conversion result (adcr register value) and power-fail comparison threshold register (pft) va lue are compared. intad is generated only when a comparative condition has been matched. figure 13-1. block diag ram of a/d converter av ref av ss intad adcs bit 3 ads2 ads1 ads0 adcs fr2 fr1 adce fr0 sample & hold circuit av ss voltage comparator controller a/d conversion result register (adcr) power-fail comparison threshold register (pft) analog input channel specification register (ads) a/d converter mode register (adm) pfen pfcm power-fail comparison mode register (pfm) internal bus comparator ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 successive approximation register (sar) selector tap selector
chapter 13 a/d converter user?s manual u15947ej2v0ud 278 13.2 configuration of a/d converter the a/d converter consists of the following hardware. table 13-1. registers of a/ d converter used on software item configuration registers successive approximat ion register (sar) a/d conversion result register (adcr) a/d converter mode register (adm) analog input channel specification register (ads) power-fail comparison mode register (pfm) power-fail comparison threshold register (pft) (1) ani0 to ani7 pins these are the analog input pins of the 8- channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin by the analog input channel specification register (ads) can be used as input port pins. (2) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started, and holds the sampled anal og input voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the analog input signal. (4) voltage comparator the voltage comparator compar es the sampled analog input voltage and t he output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) a/d conversion result register (adcr) the result of a/d conversion is loa ded from the successive approximation register (sar) to this register each time a/d conversion is completed, and the adcr register hol ds the result of a/d conversion in its higher 10 bits (the lower 6 bits are fixed to 0). (7) controller when a/d conversion has been completed or when the powe r-fail detection function is used, this controller compares the result of a/d conversi on (value of the adcr register) and t he value of the power-fail comparison threshold register (pft). it generates the interrupt intad onl y if a specified comparison condition is satisfied as a result.
chapter 13 a/d converter user?s manual u15947ej2v0ud 279 (8) av ref pin this pin inputs an analog power/reference voltage to the a/ d converter. always use this pin at the same potential as that of the v dd pin even when the a/d converter is not used. the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . in the standby mode, the current flowi ng through the series resistor string can be reduced by lowering the voltage input to the av ref pin to the av ss level. (9) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (10) a/d converter mode register (adm) this register is used to set the conversion time of the analog input signal to be conver ted, and to start or stop the conversion operation. (11) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (12) power-fail comparis on mode register (pfm) this register is used to set the power-fail monitor mode. (13) power-fail comparison threshold register (pft) this register is used to set the threshold value that is to be compared with the value of the a/d conversion result register (adcr).
chapter 13 a/d converter user?s manual u15947ej2v0ud 280 13.3 registers used in a/d converter the a/d converter uses the following five registers. ? ? ? ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 281 (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-2. format of a/d converter mode register (adm) 144 s 120 s 96 s 72 s 60 s 48 s adce 0 0 fr0 fr1 fr2 0 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 conversion time selection note 1 288/f x 240/f x 192/f x 144/f x 120/f x 96/f x setting prohibited fr2 0 0 0 1 1 1 other than above fr1 0 0 1 0 0 1 fr0 0 1 0 0 1 0 <0> 1 2 3 4 5 6 <7> adm address: ff28h after reset: 00h r/w symbol ? ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 282 table 13-2. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only reference voltage generator consumes power) 1 0 conversion mode (reference voltage generator operation stopped note ) 1 1 conversion mode (reference voltage generator operates) note data of first conversion cannot be used. figure 13-3. timing chart when boost reference voltage generator is used adce boost reference voltage adcs conversion operation conversion operation conversion stopped conversion waiting boost reference voltage generator: operating note note the time from the rising of the adce bi t to the falling of the adcs bit must be 14
chapter 13 a/d converter user?s manual u15947ej2v0ud 283 (2) analog input channel specification register (ads) this register specifies the input port of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-4. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads0 0 1 0 1 0 1 0 1 ads1 0 0 1 1 0 0 1 1 ads2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ads address: ff29h after reset: 00h r/w symbol cautions 1. be sure to clea r bits 3 to 7 of ads to 0. 2. if data is written to ads, a wait cycle is gene rated. do not write data to ads when the cpu is operating on the subsystem clock and the x1 input clock is stopped. for details, see chapter 35 cautions for wait.
chapter 13 a/d converter user?s manual u15947ej2v0ud 284 (3) a/d conversion result register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower six bits are fixed to 0. each time a/d conversion ends, the conversion resu lt is loaded from the successive appr oximation register, and is stored in adcr in order starting from the most significant bit (msb) . ff09h indicates the higher 8 bits of the conversion result, and ff08h indicates the lower 2 bits of the conversion result. adcr can be read by a 16-bit memory manipulation instruction. reset input makes adcr undefined. figure 13-5. format of a/d con version result register (adcr) symbol address: ff08h, ff09h after reset: undefined r ff09h ff08h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm) and analog input channel specification register (ads), the contents of adcr may b ecome undefined. read the conversion result following con version completion before writing to adm and ads. using timing other than the above may cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is ge nerated. do not read data from adcr when the cpu is operating on the subsystem clock and the x1 input clock is stoppe d. for details, see chapter 35 cautions for wait.
chapter 13 a/d converter user?s manual u15947ej2v0ud 285 (4) power-fail comparison mode register (pfm) the power-fail comparison mode regist er (pfm) is used to compare the a/ d conversion result (value of the adcr register) and the value of the power-f ail comparison threshold register (pft). pfm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 13-6. format of power-fail comparison mode register (pfm) 0 0 0 0 0 0 pfcm pfen power-fail comparison enable stops power-fail comparison (used as a normal a/d converter) enables power-fail comparison (used for power-fail detection) pfen 0 1 power-fail comparison mode selection interrupt request signal (intad) generation no intad generation intad generation no intad generation higher 8 bits of adcr
chapter 13 a/d converter user?s manual u15947ej2v0ud 286 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion using the analog input channel specification register (ads). <2> set adce to 1 and wait for 14 ? ? ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 287 figure 13-8. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to one of the adm, analog input channel specif ication register (ads), power-fail comparison mode register (pfm), or power-fail comparison threshold regist er (pft) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset input makes the a/d conversion re sult register (adcr) undefined.
chapter 13 a/d converter user?s manual u15947ej2v0ud 288 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in the a/d conversion result register (adcr)) is shown by the following expression. sar = int ( ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 289 13.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d co nversion is executed. in addition, the following two functions can be selected by setting of bit 7 (pfen) of the power-fail comparison mode register (pfm). ? normal 10-bit a/d converter (pfen = 0) ? power-fail detection function (pfen = 1) (1) a/d conversion operation (when pfen = 0) by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 0, t he a/d conversion operation of the volt age, which is applied to the analog input pin specified by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr), and an interrupt request signal (intad) is generated. once the a/ d conversion has started and when one a/d conversion has been completed, the next a/ d conversion operation is immediately started. the a/d conversion operations are repeated until new data is written to ads. if adm, ads, the power-fail comparison mode register (p fm), and the power-fail comparison threshold register (pft) are rewritten during a/d conversion, the a/d conversion operation under execution is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result is undefined. figure 13-10. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped a/d conversion adcr intad (pfen = 0) conversion is stopped conversion result is not retained remarks 1. n = 0 to 7 2. m = 0 to 7
chapter 13 a/d converter user?s manual u15947ej2v0ud 290 (2) power-fail detection f unction (when pfen = 1) by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1 and bit 7 (pfen) of the power-fail comparison mode register (pfm) to 1, the a/d conversion operation of the vo ltage applied to the analog input pin specified by the analog input channel spec ification register (ads) is started. when the a/d conversion has been completed, the result of the a/d conversion is st ored in the a/d conversion result register (adcr), the values are compared with power-fail comparison threshold register (pft), and an interrupt request signal (intad) is generated under the condition specified by bit 6 (pfcm) of pfm. <1> when pfen = 1 and pfcm = 0 the higher 8 bits of adcr and pft values are co mpared when a/d conversion ends and intad is only generated when the higher 8 bits of adcr
chapter 13 a/d converter user?s manual u15947ej2v0ud 291 the setting methods are described below. ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 292 13.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a
chapter 13 a/d converter user?s manual u15947ej2v0ud 293 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? ? ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 294 13.6 cautions for a/d converter (1) operating current in standby mode the a/d converter stops operating in the standby mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) of the a/d converter mode register (adm) to 0. figure 13-18 shows the circuit configurati on of the series resistor string. figure 13-18. circuit configuration of series resistor string av ref av ss p-ch series resistor string adcs (2) input range of ani0 to ani7 observe the rated range of the ani0 to ani7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result register (adcr) write and adcr read by instruction upon the end of conversion adcr read has priority. after the read operation, the new conversion result is written to adcr. <2> conflict between adcr write and a/d converter mo de register (adm) write or analog input channel specification register (ads) wr ite upon the end of conversion adm or ads write has priority. adcr write is not pe rformed, nor is the conversion end interrupt signal (intad) generated.
chapter 13 a/d converter user?s manual u15947ej2v0ud 295 (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani7. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 13-19, to reduce noise. figure 13-19. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/p20 to ani7/p27 <1> the analog input pins (ani0 to ani7) are also used as input port pins (p20 to p27). when a/d conversion is performed with any of an i0 to ani7 selected, do not access port 2 while conversion is in progress; otherwise th e conversion resolution may be degraded. <2> if a digital pulse is applied to the pins adjacent to th e pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. since only the leakage current flows other than during sa mpling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, howeve r, it is recommended to make the output impedance of the analog input source 10 k ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 296 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 13-20. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 7 2. m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 14
chapter 13 a/d converter user?s manual u15947ej2v0ud 297 (11) a/d converter sampling time a nd a/d conversion start delay time the a/d converter sampling time differs depending on the se t value of the a/d converter mode register (adm). the delay time exists until actual sampling is st arted after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 13-21 and table 13-3. figure 13-21. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time conversion time a/d conversion start delay time sampling time sampling timing intad adcs ? ? ?
chapter 13 a/d converter user?s manual u15947ej2v0ud 298 (13) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 13-22. internal equi valent circuit of anin pin anin c1 c2 c3 r1 r2 table 13-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? ? ? ?
user?s manual u15947ej2v0ud 299 chapter 14 serial interface uart0 14.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. for details, see 14.4.2 asynchronous seri al interface (uart) mode and 14.4.3 dedicated baud rate generator . ? ? ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 300 14.2 configuration of serial interface uart0 serial interface uart0 consis ts of the following hardware. table 14-1. configurati on of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface o peration mode register 0 (asim0) asynchronous serial interface recepti on error status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 1 (pm1) port register 1 (p1)
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 301 figure 14-1. block diagra m of serial interface uart0 t x d0/ sck10/p10 intst0 r x d0/ si10/p11 intsr0 f x /2 5 f x /2 3 f x /2 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) 8-bit timer/ event counter 50 output registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit output latch (p10) pm10 7 7
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 302 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data conv erted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is tran sferred to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the rece ive data is not transferred to rxb0. rxb0 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset input or power0 = 0 se ts this register to ffh. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. txs0 can be written by an 8-bit memory manipulatio n instruction. this register cannot be read. reset input, power0 = 0, or txe0 = 0 sets this register to ffh. caution do not write the next tran smit data to txs0 before the tr ansmission completion interrupt signal (intst0) is generated.
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 303 14.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following five registers. ? ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 304 figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface reception error status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. at startup, set power0 to 1 and then set txe0 to 1. to stop the op eration, clear txe0 to 0, and then clear power0 to 0. 2. at startup, set power0 to 1 and then set rxe0 to 1. to stop the operation, clear rxe0 to 0, and then clear power0 to 0. 3. set power0 to 1 and then set rxe0 to 1 wh ile a high level is input to the rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 wh ile a low level is input, reception is started. 4. txe0 and rxe0 are sync hronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two clocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or recepti on circuit may not be initialized. 5. clear the txe0 and rxe0 bits to 0 be fore rewriting the ps01, ps00, and cl0 bits. 6. make sure that txe0 = 0 when rewriting th e sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit. 7. be sure to set bit 0 to 1.
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 305 (2) asynchronous serial interface recepti on error status register 0 (asis0) this register indicates an error status on completion of reception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register is read-only by an 8-bit memory manipulation instruction. reset input clears this re gister to 00h if bit 7 (power0) and bit 5 (rxe 0) of asim0 = 0. 00 h is read when this register is read. figure 14-3. format of asynchronous serial inte rface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 status flag indicating parity error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface operati on mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, re gardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the cpu is operating on the subsystem clock and the x1 input clock is stoppe d. for details, see chapter 35 cautions for wait.
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 306 (3) baud rate generator c ontrol register 0 (brgc0) this register selects the base clock of serial interf ace uart0 and the division value of the 5-bit counter. brgc0 can be set by an 8-bit memory manipulation instruction. reset input sets this register to 1fh. figure 14-4. format of baud rate ge nerator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 tps01 tps00 base clock (f xclk0 ) selection 0 0 tm50 output note 0 1 f x /2 (5 mhz) 1 0 f x /2 3 (1.25 mhz) 1 1 f x /2 5 (312.5 khz) mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 307 remarks 1. f xclk0 : frequency of base clock selected by the tps01 and tps00 bits 2. f x : x1 input clock oscillation frequency 3. k: value set by the mdl04 to md l00 bits (k = 8, 9, 10, ..., 31) 4.
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 308 14.4 operation of serial interface uart0 serial interface uart0 has the following two modes. ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 309 14.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 310 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. figure 14-6. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 311 (b) parity types and operation the parity bit is used to detect a bit error in communica tion data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 312 (c) transmission the t x d0 pin outputs a high level when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1. if bit 6 (txe0) of asim0 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to tr ansmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatica lly appended to the data. when transmission is started, the start bit is output from the t x d0 pin, followed by t he rest of the data in order starting from the lsb. when transmission is co mpleted, the parity and stop bits set by asim0 are appended and a transmission completion inte rrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 14-8 shows the timing of the transmission comp letion interrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 14-8. transmission comple tion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 313 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator st arts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 14-9). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, recept ion is started, and serial data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the st op bit has been received, the reception completion interrupt (intsr0) is generated and t he data of rxs0 is written to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (int sr0) is generated after completion of reception. figure 14-9. reception completi on interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. be sure to read receive buffer register 0 (rxb0) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 0 (asis0) before reading rxb0.
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 314 (e) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 0 (asis0) is set as a result of data reception, a reception error interrupt request (intsr0) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis0 in the reception error interrupt servicing (intsr0) (see figure 14-3 ). the contents of asis0 are reset to 0 when asis0 is read. table 14-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14- 10, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-10. noise filter circuit internal signal b internal signal a match detector in base clock r x d0/si10/p11 q in ld_en q
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 315 14.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a sour ce clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 316 (2) generation of serial clock a serial clock can be generated by using baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value of the 5-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 317 (3) example of setting baud rate table 14-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] tps01, tps00 k calculated value err[%] 2400 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 318 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 14-12. permissible baud rate range during reception fl 1 data frame (11 ?
chapter 14 serial interface uart0 user?s manual u15947ej2v0ud 319 minimum permissible data frame length: flmin = 11 ? ? ? ? ? ? ? ? ? ? ?
user?s manual u15947ej2v0ud 320 chapter 15 serial interface uart6 15.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 15.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 15.4.2 asynchronous seri al interface (uart) mode and 15.4.3 dedicated baud rate generator . ? two-pin configuration t x d6: transmit data output pin r x b6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? twelve operating clock inputs selectable ? msb- or lsb-first communication selectable ? inverted transmission operation ? synchronous break field transmission from 13 to 20 bits ? more than 11 bits can be identified for synchronous break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only th e transmission side and not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops ope rating, and holds the value i mmediately before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. how ever, the operation is not guara nteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. if data is continuously transmitted, the communication timi ng from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the recepti on side initializes the timing when it has detected a start bit. do not use the contin uous transmission function if the interface is incorporated in lin.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 321 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 322 figure 15-2. lin reception operation sleep bus 13 bits note 2 sf reception id reception data reception data reception data reception note 5 note 3 note 1 note 4 wakeup signal frame synchronous break field synchronous field indent field data field data field checksum field rx6 sbf reception reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable notes 1. the wakeup signal is detected at the edge of the pin, and enables uart6 and sets the sbf reception mode. 2. reception continues until the stop bit is detected. when an sbf wit h low-level data of 11 bits or more has been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if an sbf with low-level da ta of less than 11 bits has been detected, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. 3. if sbf reception has been completed correctly, an interrupt signal is output. this sbf reception completion interrupt enables the capture timer. detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of ua rt communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. 4. calculate the baud rate error from the bit length of the synchronous field, disable uart6 after sf reception, and then re-set baud rate gen erator control register 6 (brgc6). 5. distinguish the checksum field by software. also perform processi ng by software to initialize uart6 after reception of the checksum field an d to set the sbf reception mode again. to perform a lin receive operation, use a conf iguration like the one shown in figure 15-3. the wakeup signal transmitted from the lin master is re ceived by detecting the edge of the external interrupt (intp0). the length of the synchronous field transmitted from the lin master can be measured using the external event capture operation of 16-bit ti mer/event counter 00, and the bau d rate error can be calculated. the input signal of the reception port input (rxd6) ca n be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input switch control (isc0/isc1), without co nnecting rxd6 and intp0/ti000 externally.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 323 figure 15-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p14/rxd6 p120/intp0 p00/ti000 port input switch control (isc0) 0: select intp0 (p120) 1: select rxd6 (p14) port mode (pm14) output latch (p14) port mode (pm120) output latch (p120) port input switch control (isc1) 0: select ti000 (p00) 1: select rxd6 (p14) selector selector selector selector selector port mode (pm00) output latch (p00) remark isc0, isc1: bits 0 and 1 of the input switch control register (isc) (see figure 15-11 ) the peripheral functions used in the lin communication operation are shown below. ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 324 15.2 configuration of serial interface uart6 serial interface uart6 consis ts of the following hardware. table 15-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 1 (pm1) port register 1 (p1)
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 325 figure 15-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ p13 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/ p14 ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 8-bit timer/ event counter 50 output 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p13) pm13 8 selector note selectable with input switch control register (isc).
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 326 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (rxs6). if the data length is set to 7 bits, data is transferred as follows. ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 327 15.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 note 3 enables operation of the internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. 3. operation of the 8-bit counter out put is enabled at the second base clock after 1 is written to the power6 bit.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 328 figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set txe6 to 1. to stop the op eration, clear txe6 to 0, and then clear power6 to 0. 2. at startup, set power6 to 1 and then set rxe6 to 1. to stop the operation, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 wh ile a high level is input to the rxd6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 5. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 6. make sure that txe6 = 0 wh en rewriting the sl6 bit. recep tion is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 7. make sure that rxe6 = 0 when rewriting the isrm6 bit.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 329 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset input clears this re gister to 00h if bit 7 (power6) and bit 5 (rxe 6) of asim6 = 0. 00 h is read when this register is read. figure 15-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and the x1 input clock is stoppe d. for details, see chapter 35 cautions for wait.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 330 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset input clears this register to 00h if bi t 7 (power6) and bit 6 (txe6) of asim6 = 0. figure 15-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0? after genera tion of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 331 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is writ ten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection 0 0 0 0 f x (10 mhz) 0 0 0 1 f x /2 (5 mhz) 0 0 1 0 f x /2 2 (2.5 mhz) 0 0 1 1 f x /2 3 (1.25 mhz) 0 1 0 0 f x /2 4 (625 khz) 0 1 0 1 f x /2 5 (312.5 khz) 0 1 1 0 f x /2 6 (156.25 khz) 0 1 1 1 f x /2 7 (78.13 khz) 1 0 0 0 f x /2 8 (39.06 khz) 1 0 0 1 f x /2 9 (19.53 khz) 1 0 1 0 f x /2 10 (9.77 khz) 1 0 1 1 tm50 output note other than above setting prohibited note to select the output of tm50 as t he base clock, start the operation by setting 8-bit timer/event counter 50 so that the duty is 50% of t he output in the pwm mode (bit 6 (tmc506) of the tmc50 register = 1), and then set tps63, tps62, tps61, and tps60 to 1, 0, 1, and 1, respectively. it is not necessary to enable the to50 pin as a timer output pin (bit 0 (toe 50) of the tmc register may be 0 or 1). cautions 1. when the ring -osc clock is selected as th e clock to be supplied to the cpu, the clock of the ring-osc oscillator is divided and supplied as the count clock. if the base clock is the ring- osc clock, the operation of serial interface uart6 is not guaranteed. 2. make sure power6 = 0 when rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 332 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 15-9. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 333 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). note, however, that comm unication is started by the refresh operation because bit 6 (sbrt6) of asicl6 is cleared to 0 when communication is completed (when an interrupt signal is generated). figure 15-10. format of asynchronous serial interface control register 6 (asicl6) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 0 1 0 1 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 334 (7) input switch control register (isc) the input switch control register (isc) is used to receiv e a status signal transmitted from the master during lin (local interconnect network) reception. the input signal is switched by setting isc. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 15-11. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p00) 1 rxd6 (p14) isc0 intp0 input source selection 0 intp0 (p120) 1 rxd6 (p14) (8) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/txd3 pin for serial interface data out put, clear pm13 to 0 and set the output latch of p13 to 1. when using the p14/rxd6 pin for serial interface data input, set pm14 to 1. the output latch of p14 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 15-12. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 335 15.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 336 15.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? ? ? ? ? ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 337 the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm13 p13 pm14 p14 uart6 operation txd6/p13 rxd6/p14 0 0 0 note note note note stop p13 p14 0 1 note note 1 reception p13 rxd6 1 0 0 1 note note transmission txd6 p14 1 1 1 0 1 1 transmission/ reception txd6 rxd6 note can be set as port function. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm1: port mode register p1: port output latch
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 338 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. figure 15-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 339 figure 15-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 340 (b) parity types and operation the parity bit is used to detect a bit error in communica tion data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 wh en the device is inco rporated in lin. (i) even parity ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 341 (c) normal transmission the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1. if bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to tr ansmit buffer register 6 (txb6). the start bit, parity bit, and stop bit are automatica lly appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the data is sequentially out put from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission co mpletion interrupt reques t (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 15-15 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 15-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 342 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference the asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asis register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 a nd txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. 2. when the device is incorp orated in a lin, the continuous transmission function cannot be used. make sure that a synchronous serial interface tran smission status register 6 (asif6) is 00h before writin g transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transmission unit upon completion of continuous transmission, be sure to check that the txsf6 flag is ?0? afte r generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmission, an ove rrun error may occur, which means that the next transmission was completed before exe cution of intst6 interrupt servicing after transmission of one data frame. an ove rrun error can be detected by developing a program that can count the number of transmit data and by refere ncing the txsf6 flag.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 343 figure 15-16 shows an example of the continuous transmission processing flow. figure 15-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag)
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 344 figure 15-17 shows the timing of starting continuous transmission, and figure 15-18 shows the timing of ending continuous transmission. figure 15-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 345 figure 15-18. timing of ending continuous transmission t x d6 start intst6 data (n ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 346 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 15-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6 /intsre6) is generated on completion of reception. figure 15-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. be sure to read receive buffer register 6 (rxb6) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6.
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 347 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (see figure 15-6 ). the contents of asis6 are reset to 0 when asis6 is read. table 15-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynchronous se rial interface operation mode register 6 (asim6) to 0. figure 15-20. reception error interrupt 1. if isrm6 is cleared to 0 (reception completion in terrupt (intsr6) and erro r interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 348 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 15- 21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 15-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p14 q in ld_en q (h) sbf transmission when the device is incorporated in lin, the sbf (syn chronous break field) transmission control function is used for transmission. for the tr ansmission operation of lin, see figure 15-1 lin transmission operation . sbf transmission is used to transmit an sbf length that is a low-level widt h of 13 bits or more by adjusting the baud rate value of the ordi nary uart transmission function. [setting method] transmit 00h by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. this enables a low-level transmi ssion of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). adjust the baud rate value to adjust this 10 -bit low level to the targeted sbf length. example if lin is to be transmitted under the following conditions ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 349 if the number of bits set by brgc6 runs short, adjus t the number of bits by setting the base clock of uart6. figure 15-22. example of setting proced ure of sbf transmission (flowchart) start read brgc6 register and save current set value of brgc6 register to general- purpose register. clear txe6 and rxe6 bits of asim6 register to 0 (to disable transmission/ reception). set value to brgc6 register to realize desired sbf length. set character length of data to 8 bits and parity to 0 or even using asim6 register. set txe6 bit of asim6 register to 1 to enable transmission. set txb6 register to "00h" and start transmission. intst6 occurred? no yes clear txe6 and rxe6 bits of asim6 register to 0. rewrite saved brgc6 value to brgc6 register. re-set ps61 bit, ps60 bit, and cl6 bit of asim6 register to desired value. set txe6 bit of asim6 register to 1 to enable transmission. end figure 15-23. sbf transmission t x d6 intst6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 350 (i) sbf reception when the device is incorporated in lin, the sbf (syn chronous break field) reception control function is used for reception. for the re ception operation of lin, see figure 15-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is st arted, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. wh en the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt reques t (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatical ly cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of as ynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the wi dth of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been re ceived, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 15-24. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 351 15.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 352 figure 15-25. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 353 (2) generation of serial clock a serial clock can be generated by using clock selecti on register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 354 (3) example of setting baud rate table 15-4. set data of baud rate generator f x = 10.0 mhz f x = 8.38 mhz f x = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 109 601 0.11 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 109 1201 0.11 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 109 2403 0.11 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 109 4805 0.11 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 109 9610 0.11 1h 109 9610 0.11 10400 2h 120 10417 0.16 2h 101 10371 0.28 1h 101 10475 ? ? ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 355 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 15-26. permissible baud rate range during reception fl 1 data frame (11 ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 356 minimum permissible data frame length: flmin = 11 ? ? ? ? ? ? ? ? ? ? ? ?
chapter 15 serial interface uart6 user?s manual u15947ej2v0ud 357 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 15-27. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11
user?s manual u15947ej2v0ud 358 chapter 16 serial interfaces csi10 and csi11 the ? ?
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 359 16.2 configuration of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 consist of the following hardware. table 16-1. configuration of serial interfaces csi10 and csi11 item configuration registers transmit buffer register 1n (sotb1n) serial i/o shift re gister 1n (sio1n) transmit controller clock start/stop controller & clock phase controller control registers serial operation mode register 1n (csim1n) serial clock selection register 1n (csic1n) port mode register 0 (pm0) or port mode register 1 (pm1) port register 0 (p0) or port register 1 (p1) remark n = 0:
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 360 figure 16-2. block diagram of serial interface csi11 (
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 361 16.3 registers controlling serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 are cont rolled by the following four registers. ? ? ? ?
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 362 figure 16-4. format of serial oper ation mode register 11 (csim11) address: ff88h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim11 csie11 trmd11 sse11 dir11 0 0 0 csot11 csie11 operation control in 3-wire serial i/o mode 0 disables operation note 2 and asynchronously resets the internal circuit note 3 . 1 enables operation trmd11 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode sse11 notes 6, 7 ssi11 pin use selection 0 ssi11 pin is not used 1 ssi11 pin is used dir11 note 8 first bit specification 0 msb 1 lsb csot11 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. when using as a general-purpose port, see caution 3 of figure 16-6 and table 16-2 . 3. bit 0 (csot11) of csim11 and serial i/o shift register 11 (sio11) are reset. 4. do not rewrite trmd11 when csot11 = 1 (during serial communication). 5. the so11 output is fixed to the low level when trmd 11 is 0. reception is started when data is read from sio11. 6. do not rewrite sse11 when csot11 = 1 (during serial communication). 7. before setting this bit to 1, fix the ssi11 pin input level to 0 or 1. 8. do not rewrite dir11 when csot11 = 1 (during serial communication).
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 363 (2) serial clock selecti on register 1n (csic1n) this register specifies the timing of the data transmission/reception and sets the serial clock. csic1n can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. remark n = 0:
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 364 cautions 1. when the ring-osc clo ck is selected as the clock supplied to the cpu, the clock of the ring- osc oscillator is divided and supp lied as the serial clock. at th is time, the operation of serial interface csi10 is not guaranteed. 2. do not write to csic10 while csie10 = 1 (operation enabled). 3. clear ckp10 to 0 to use p10/sck10/txd0, p11/si10/rxd0, and p12/so10 as general-purpose port pins. 4. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 365 figure 16-6. format of serial clo ck selection register 11 (csic11) address: ff89h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic11 0 0 0 ckp11 dap11 cks112 cks111 cks110 ckp11 dap11 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck11 so11 si11 input timing 4 cks112 cks111 cks110 csi11 se rial clock selection mode 0 0 0 f x /2 (5 mhz) master mode 0 0 1 f x /2 2 (2.5 mhz) master mode 0 1 0 f x /2 3 (1.25 mhz) master mode 0 1 1 f x /2 4 (625 khz) master mode 1 0 0 f x /2 5 (312.5 khz) master mode 1 0 1 f x /2 6 (156.25 khz) master mode 1 1 0 f x /2 7 (78.13 khz) master mode 1 1 1 external clock input to sck11 slave mode cautions 1. when the ring-osc clo ck is selected as the clock supplied to the cpu, the clock of the ring- osc oscillator is divided and supp lied as the serial clock. at th is time, the operation of serial interface csi11 is not guaranteed. 2. do not write to csic11 while csie11 = 1 (operation enabled). 3. clear ckp11 to 0 to use p0 2/so11, p03/si11, and p04/sck11 as general-purpose port pins. 4. the phase type of the data clock is type 1 after reset. remarks 1. figures in parentheses are for operation with fx = 10 mhz 2. f x : x1 input clock oscillation frequency
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 366 (3) port mode registers 0 and 1 (pm0, pm1) these registers set port 0 and 1 input/output in 1-bit units. when using p10/sck10 and p04/sck11 note as the clock output pins of t he serial interface, and p12/so10 and p02/so11 note as the data output pins, clear pm10, pm04, pm12, pm02, and the output latches of p10, p04, p12, and p02 to 0. when using p10/sck10 and p04/sck11 note as the clock input pins of the serial interface, p11/si10/rxd0 and p03/si11 note as the data input pins, and p05/ ssi11/ti001 as the chip select i nput pin, set pm10, pm04, pm11, pm03, and pm05 to 1. at this time, the output latches of p10, p04, p11, p03, and p05 may be 0 or 1. pm0 and pm1 can be set by a 1-bit or 8- bit memory manipulation instruction. reset input sets these registers to ffh. note
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 367 16.4 operation of serial interfaces csi10 and csi11 serial interfaces csi10 and csi11 can be used in the following two modes. ? ? ? ?
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 368 16.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is used for connecting peripheral ics and display controll ers with a clocked serial interface. in this mode, communication is executed by using three li nes: the serial clock (sck1n), serial output (so1n), and serial input (si1n) lines. (1) registers used ? ? ? ?
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 369 the relationship between the register settings and pins is shown below. table 16-2. relationship between register settings and pins (1/2) (a) serial interface csi10 pin function csie10 trmd10 pm11 p11 pm12 p12 pm10 p10 csi10 operation si10/rxd0/ p11 so10/p12 sck10/ txd0/p10 0 note 1 note 1 note 1 note 1 note 1 note 1 stop rxd0/p11 p12 txd0/ p10 note 2 1 0 1 note 1 note 1 1 slave reception note 3 si10 p12 sck10 (input) note 3 1 1 note 1 note 1 0 0 1 slave transmission note 3 rxd0/p11 so10 sck10 (input) note 3 1 1 1 0 0 1 slave transmission/ reception note 3 si10 so10 sck10 (input) note 3 1 0 1 note 1 note 1 0 1 master reception si10 p12 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission rxd0/p11 so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p10/sck10/txd0 as port pins, clear ckp10 to 0. 3. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. remark : don?t care csie10: bit 7 of serial operation mode register 10 (csim10) trmd10: bit 6 of csim10 ckp10: bit 4 of serial clock selection register 10 (csic10) cks102, cks101, cks100: bits 2 to 0 of csic10 pm1: port mode register p1: port output latch
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 370 table 16-2. relationship between register settings and pins (2/2) (b) serial interface csi11 (
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 371 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the dat a is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd1n) of serial operation mode register 1n (csim1n) is 1. transmission/reception is started when a value is writt en to transmit buffer register 1n (sotb1n). in addition, data can be received when bit 6 (trmd1n) of seri al operation mode register 1n (csim1n) is 0. reception is started when dat a is read from serial i/o shift register 1n (sio1n). however, communication is performed as follows if bit 5 (s se11) of csim11 is 1 when serial interface csi11 is in the slave mode. <1> low level input to the ssi11 pin
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 372 figure 16-9. timing in 3-wire serial i/o mode (1/2) (1) transmission/reception timing (t ype 1; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 0, sse11 = 1 note ) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb1n. sck1n sotb1n sio1n csot1n csiif1n so1n si1n (receive aah) read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0:
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 373 figure 16-9. timing in 3-wire serial i/o mode (2/2) (2) transmission/reception timing (t ype 2; trmd1n = 1, dir1n = 0, ckp1n = 0, dap1n = 1, sse11 = 1 note ) abh 56h adh 5ah b5h 6ah d5h sck1n sotb1n sio1n csot1n csiif1n so1n si1n (input aah) aah 55h (communication data) 55h is written to sotb1n. read/write trigger intcsi1n ssi11 note note the sse11 flag and ssi11 pin are available only for serial interface csi11, and are used in the slave mode. remark n = 0:
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 374 figure 16-10. timing of clock/data phase (a) type 1; ckp1n = 0, dap1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (b) type 2; ckp1n = 0, dap1n = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (c) type 3; ckp1n = 1, dap1n = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n (d) type 4; ckp1n = 1, dap1n = 1 d7 d6 d5 d4 d3 d2 d1 d0 sck1n so1n writing to sotb1n or reading from sio1n si1n capture csiif1n csot1n remark n = 0:
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 375 (3) timing of output to so1n pin (first bit) when communication is started, the value of transmit buffe r register 1n (sotb1n) is output from the so1n pin. the output operation of the first bit at this time is described below. figure 16-11. output operation of first bit (1) when ckp1n = 0, dap1n = 0 (or ckp1n = 1, dap1n = 0) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit output latch the first bit is directly latched by the sotb1n register to the output latch at the falling (or rising) edge of sck1n, and output from the so1n pin via an output selector. th en, the value of the sotb1n register is transferred to the sio1n register at the next rising (or fa lling) edge of sck1n, and shifted one bit. at the same time, the first bit of the receive data is stored in the s io1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the output latch at the next falling (or rising) edge of sck1n, and the data is output from the so1n pin. (2) when ckp1n = 0, dap1n = 1 (or ckp1n = 1, dap1n = 1) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n first bit 2nd bit 3rd bit output latch the first bit is directly latched by the sotb1n register at the falling edge of the write signal of the sotb1n register or the read signal of the sio1n register, and output from the so1n pin via an output selector. then, the value of the sotb1n register is transfe rred to the sio1n register at the next falling (or rising) edge of sck1n, and shifted one bit. at the same time, the first bit of the rece ive data is stored in the sio1n register via the si1n pin. the second and subsequent bits are latc hed by the sio1n register to the out put latch at the next rising (or falling) edge of sck1n, and the data is output from the so1n pin. remark n = 0:
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 376 (4) output value of so1n pin (last bit) after communication has been completed, the so1n pin holds the output value of the last bit. figure 16-12. output value of so1n pin (last bit) (1) type 1; when ckp1n = 0 and dap1n = 0 (or ckp1n = 1, dap1n = 0) sck1n sotb1n sio1n so1n writing to sotb1n or reading from sio1n (
chapter 16 serial interfaces csi10 and csi11 user?s manual u15947ej2v0ud 377 (5) so1n output the status of the so1n output is as follows if bit 7 (csie1n) of serial operation mode register 1n (csim1n) is cleared to 0. table 16-3. so1n output status trmd1n dap1n dir1n so1n output trmd1n = 0 note ? ? ?
user?s manual u15947ej2v0ud 378 chapter 17 serial interface csia0 17.1 functions of serial interface csia0 serial interface csia0 has the following three modes. ? ? ? ? ? ? ? ? ? ? ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 379 17.2 configuration of serial interface csia0 serial interface csia0 consists of the following hardware. table 17-1. configuration of serial interface csia0 item configuration registers serial i/o shi ft register 0 (sioa0) automatic data transfer address count register 0 (adtc0) control registers serial operation mode specification register 0 (csima0) serial status register 0 (csis0) serial trigger register 0 (csit0) divisor selection register 0 (brgca0) automatic data transfer address point specification register 0 (adtp0) automatic data transfer interval specification register 0 (adti0) port mode register 14 (pm14) port register 14 (p14)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 380 figure 17-1. block diagram of serial interface csia0 internal bus baud rate generator f x /6 to f x /32 selector master0 p145 p142 pm142 pm145 pm144 scka0/p142 busy0/p141 stb0/p145 soa0/p144 sia0/p143 dir0 ate0 6-bit counter buffer ram interrupt generator serial transfer controller atm0 serial clock counter stbe0 busye0 atstp0 atsta0 busylv0 erre0 errf0 tsf0 automatic data transfer address point specification register 0 (adtp0) automatic data transfer address count register 0 (adtc0) divisor selection register 0 (brgca0) serial i/o shift register 0 (sioa0) automatic data transfer interval specification register 0 (adti0) intacsi p144 3 4 2 serial trigger register 0 (csit0) serial status register 0 (csis0) f x rxae txae
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 381 (1) serial i/o shift register 0 (sioa0) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 0). writing transmit data to sioa0 starts the communication. in addition, after a communication completion interrupt r equest (intacsi) is output (bit 0 (tsf0) of serial status register 0 (csis0) = 0), data can be received by reading data from sioa0. this register can be written or read by an 8-bit memory manipulation instruction. however, writing to sioa0 is prohibited when bit 0 (tsf0) of seri al status register 0 (csis0) = 1. reset input clears this register to 00h. cautions 1. a communication opera tion is started by writing to sioa0. consequently, when transmission is disabled (bit 3 (txea0) of cs ima0 = 0), write dummy data to the sioa0 register to start the communication operati on, and then perform a receive operation. 2. do not write data to sioa0 while the au tomatic transmit/receive function is operating. (2) automatic data transfer a ddress count register 0 (adtc0) this is a register used to indicate buffer ram addresses during automatic transfer. when automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading adtc0 register value. this register can be read by an 8-bi t memory manipulation instruction. reset input clears this register to 00h. however, re ading from adtc0 is prohibi ted when bit 0 (tsf0) of serial status register 0 (csis0) = 1. figure 17-2. format of automatic data tr ansfer address count register 0 (adtc0) 0 adtc0 0 0 adtc04 adtc03 adtc02 adtc01 adtp00 address: ff97h after reset: 00h r symbol 43 21 0 6 75 17.3 registers controlling serial interface csia0 serial interface csia0 is controlled by the following eight registers. ? ? ? ? ? ? ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 382 (1) serial operation mode speci fication register 0 (csima0) this is an 8-bit register used to cont rol the serial communication operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 17-3. format of serial operation mode specification register 0 (csima0) csiae0 csia0 operation disabled (soa0: low level, scka0: high level) and asynchronously resets the internal circuit note . csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 1-byte communication mode automatic communication mode ate0 0 1 control of automatic communication operation enable/disable single transfer mode (stops at the address specified by the adtp0 register) repeat transfer mode (after transfer is complete, clear the adtc0 register to 00h to resume transfer) atm0 0 1 automatic communication mode specification slave mode (synchronous with scka0 input clock) master mode (synchronous with internal clock) master0 0 1 csia0 master/slave mode specification transmit operation disabled (soa0: low level) txea0 0 1 control of transmit operation enable/disable receive operation disabled receive operation enabled rxea0 0 1 control of receive operation enable/disable msb lsb dir0 0 1 first bit specification address: ff90h after reset: 00h r/w transmit operation enabled symbol < > < > < > note automatic data transfer address count register 0 (adtc0 ), serial trigger register 0 (csit0), serial i/o shift register 0 (sioa0), and bit 0 (tsf0) of serial status register 0 (csis0) are reset. cautions 1. when csiae0 = 0, the buffer ram cannot be accessed. 2. when csiae0 is changed from 1 to 0, th e registers and bits me ntioned in note above are asynchronously initialized. to set csiae0 = 1 again, be sure to re-set the initialized registers. 3. when csiae0 is re-set to 1 after csiae0 is changed from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 383 (2) serial status register 0 (csis0) this is an 8-bit register used to control the comm unication operation and indicate status of csia0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. however, re writing csis0 is prohibited when bit 0 (tsf0) is 1. figure 17-4. format of serial st atus register 0 (csis0) (1/2) 0 csis0 symbol 0 stbe0 busye0 busylv0 erre0 errf0 tsf0 strobe output disabled strobe output enabled stbe0 notes 2, 3 0 1 strobe output enable/disable busy signal detection disabled (input via busy0 pin is ignored) busy signal detection enabled and communication wait by busy signal is executed busye0 0 1 busy signal detection enable/disable low level high level busylv0 note 4 0 1 busy signal active level setting address: ff91h after reset: 00h r/w note 1 43 21 0 6 75 notes 1. bits 0 and 1 are read-only. 2. stbe0 is valid only in master mode. 3. when stbe0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the setting of automatic data transfer interval specificatio n register 0 (adti0). that is, 10 transfer clocks are used for 1-byte transfer if adti0 = 00h is set. 4. in bit error detection by busy input, the acti ve level specified by busylv0 is detected. caution be sure to clear bits 6 and 7 to 0.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 384 figure 17-4. format of serial st atus register 0 (csis0) (2/2) error detection disabled error detection enabled erre0 note 0 1 bit error detection enable/disable  bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0  at reset input  when communication is started by setting bit 0 (atsta0) of serial trigger register 0 (csit0) to 1 or writing to sioa0. bit error detected (when erre0 = 1, the level specified by busylv0 during the data bit transfer period is detected via busy0 pin input). errf0 0 1 bit error detection flag  bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0  at reset input  at the end of the specified transfer  when transfer is stopped by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1 from the transfer start to the end of the specified transfer tsf0 0 1 transfer status detection flag note the erre0 setting is valid even when busye0 = 0. caution when tsf0 is 1, rewritin g serial operation mode specification re gister 0 (csima0), serial status register 0 (csis0), divisor sel ection register 0 (brgca0), automa tic data transfer address point specification register 0 (adtp0), automatic data transfer inte rval specification register 0 (adti0), and serial i/o shift register 0 (sioa0) ar e prohibited. however, these registers can be read and re-written to the same value. in a ddition, the buffer ram can be rewritten during transfer.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 385 (3) serial trigger register 0 (csit0) this is an 8-bit register used to control executi on/stop of automatic data tr ansfer between buffer ram and serial i/o shift register 0 (sioa0). this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. however, ma nipulate only when bit 6 (a te0) of serial operation mode specification register 0 (csima0) is 1 (manipulation prohibited when ate0 = 0). figure 17-5. format of serial trigger register 0 (csit0) 0 csit0 symbol 0 0 0 0 0 atstp0 atsta0 automatic data transfer stopped atstp0 0 1 automatic data transfer stop automatic data transfer started atsta0 0 1 automatic data transfer start address: ff92h after reset: 00h r/w 4 3 2 <1> <0> 6 75 ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 386 (4) divisor selection register 0 (brgca0) this is an 8-bit register used to select the serial clock. this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting brgca0 is prohibited. figure 17-6. format of divisor selection register 0 (brgca0) 0 brgca0 symbol 0 0 0 0 0 brgca01 brgca00 brgca01 0 0 1 1 brgca00 0 1 0 1 csia0 serial clock selection f x /6 (1.67 mhz) f x /2 3 (1.25 mhz) f x /2 4 (625 khz) f x /2 5 (312.5 khz) address: ff93h after reset: 03h r/w 43 21 0 6 75 remarks 1. figures in parentheses apply to operation with f x = 10 mhz 2. f x : x1 input clock oscillation frequency (5) automatic data transfer address point specification register 0 (adtp0) this is an 8-bit register used to specify the buffe r ram address that ends transfer during automatic data transfer (bit 6 (ate0) of serial operati on mode specification register 0 = 1). this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adtp0 is prohibited. in the 78k0/kf1, 00h to 1fh can be specified bec ause 32 bytes of buffer ram are incorporated. example when adtp0 is set to 07h 8 bytes of fa00h to fa07h are transferred. in repeat transfer mode (bit 5 (atm0) of csima0 = 1), transfer is performed repeatedly up to the address specified with adtp0. example when adtp0 is set to 07h (repeat transfer mode) transfer is repeated as fa00h to fa07h, fa00h to fa07h, ? . figure 17-7. format of automatic data transfer address point specificat ion register 0 (adtp0) 0 adtp0 0 0 adtp04 adtp03 adtp02 adtp01 adtp00 address: ff94h after reset: 00h r/w symbol 43 21 0 6 75 caution be sure to clea r bits 7 to 5 to 0.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 387 the relationship between buffer ram address values and adtp0 setting values is shown below. table 17-2. relationship between buffer ram address values and adtp0 setting values buffer ram address value adtp0 setting value buffer ram address value adtp0 setting value fa00h 00h fa10h 10h fa01h 01h fa11h 11h fa02h 02h fa12h 12h fa03h 03h fa13h 13h fa04h 04h fa14h 14h fa05h 05h fa15h 15h fa06h 06h fa16h 16h fa07h 07h fa17h 17h fa08h 08h fa18h 18h fa09h 09h fa19h 19h fa0ah 0ah fa1ah 1ah fa0bh 0bh fa1bh 1bh fa0ch 0ch fa1ch 1ch fa0dh 0dh fa1dh 1dh fa0eh 0eh fa1eh 1eh fa0fh 0fh fa1fh 1fh
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 388 (6) automatic data transfer inter val specification register 0 (adti0) this is an 8-bit register used to specify the interv al time between 1-byte communications during automatic data transfer (bit 6 (ate0) of serial operati on mode specification register 0 (csima0) = 1). set this register when in master mode (bit 4 (master0) of csima0 = 1) (setting is unnecessary in slave mode). setting in 1-byte communication mode (bit 6 (ate0) of csima0 = 0) is also valid. when the interval time specified by adti0 after the end of 1-byte communication has elapsed, an interrupt request signal (intacsi) is output. the number of clocks for t he interval can be set to between 0 and 63 clocks. this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adti0 is prohibited. figure 17-8. format of automatic data transf er interval specificatio n register 0 (adti0) 0 adti0 0 adti05 adti04 adti03 adti02 adti01 adti00 address: ff95h after reset: 00h r/w symbol 43 21 0 6 75 caution because the setting of bit 5 (stbe0) and bit 4 (busye0) of serial status register 0 (csis0) takes priority over the adti0 setting, the interval time based on the setting of stbe0 and busye0 is generated even when adt i0 is cleared to 00h. example interval time when busy signal is not generated <1> when stbe0 = 1, busye0 = 0: inter val time of two seria l clocks is generated <2> when stbe0 = 0, busye0 = 1: inter val time of one seria l clock is generated <3> when stbe0 = 1, busye0 = 1: inter val time of two seria l clocks is generated therefore, clearing stbe0 and busye0 to 0 is required to perform no-wait transfer. the specified interval time is the serial clock (specifie d by divisor selection register 0 (brgca0)) multiplied by an integer value. example when adti0 = 03h scka0 interval time of 3 clocks
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 389 (7) port mode register 14 (pm14) this register sets port 14 input/output in 1-bit units. when using p142/scka0, p144/soa0, and p145/stb0 pins as the clock output, data output, or strobe output of the serial interface, cl ear pm142, pm144, pm145, and the output latches of p142, p144, and p145 to 0. when using p141/busy0, p142/scka0, and p143/sia0 pins as the busy input, clock input, or data input of the serial interface, set pm141, pm142, and pm143 to 1. at this time, the output latches of p141, p142, and p143 may be 0 or 1. pm14 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 17-9. format of port mode register 14 (pm14) address: ff2eh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm14 1 1 pm145 pm144 pm143 pm142 pm141 pm140 pm14n p14n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 390 17.4 operation of serial interface csia0 serial interface csia0 has the following three modes.  operation stop mode  3-wire serial i/o mode ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 391 17.4.2 3-wire serial i/o mode the one-byte data transmission/reception is executed in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is cleared to 0. the 3-wire serial i/o mode is useful for connecting peripheral ics and display controllers with a clocked serial interface. in this mode, communication is executed by using three lines: serial clock (scka0), serial output (soa0), and serial input (sia0) lines. (1) registers used  serial operation mode specif ication register 0 (csima0) note 1  serial status register 0 (csis0) note 2  divisor selection register 0 (brgca0)  port mode register 14 (pm14)  port register 14 (p14) notes 1. bits 7, 6, and 4 to 1 (csiae0, ate0, master0, txea0, rxea0, and dir0) are used. setting of bit 5 (atm0) is invalid. 2. only bit 0 (tsf0) is used. the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set the brgca0 register (see figure 17-6 ) note 1 . <2> set bits 4 to 1 (master0, txea0, rxea0 , and dir0) of the csima0 register (see figure 17-3 ). <3> set bit 7 (csiae0) of the csima0 register to 1 and clear bit 6 (ate0) to 0. <4> write data to serial i/o shift register 0 (sioa0).
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 392 the relationship between the register settings and pins is shown below. table 17-3. relationship between register settings and pins pin function csiae0 ate0 master0 pm 143 p143 pm144 p144 pm142 p142 serial i/o shift register 0 operation serial clock counter operation control sia0/ p143 soa0/ p144 scka0/ p142 0 note 1 note 1 note 1 note 1 note 1 note 1 operation stopped clear p143 p144 p142 0 1 scka0 (input) 1 0 1 1 note 2 note 2 0 note 3 0 note 3 0 1 operation enabled count operation sia0 note 2 soa0 note 3 scka0 (output) notes 1. can be set as port function. 2. can be used as p143 when only transmission is performed. clear bit 2 (rxea0) of csima0 to 0. 3. can be used as p144 when only reception is performed. clear bit 3 (txea0) of csima0 to 0. remark
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 393 (2) 1-byte transmission/recep tion communication operation (a) 1-byte transmission/reception when bit 7 (csiae0) and bit 6 (ate0) of serial operatio n mode specification regist er 0 (csima0) = 1, 0, respectively, if communication data is written to serial i/o shift register 0 (sioa0), the data is output via the soa0 pin in synchronization with the scka0 fa lling edge, and then input via the sia0 pin in synchronization with scka0 falling edge, and stored in the sioa0 register in synchronization with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, communication can only be started by writing a dummy value to the sioa0 register. when communication of 1 byte is complete, an inte rrupt request signal (intacsi) is generated. in 1-byte transmission/reception, the setting of bit 5 (atm0) of csima0 is invalid. be sure to read data after confirming that bit 0 (t sf0) of serial status register 0 (csis0) = 0. figure 17-10. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at falling edge of scka0 scka0 sia0 soa0 acsiif tsf0 sioa0 write caution the soa0 pin becomes lo w level by an sioa0 write.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 394 (b) data format in the data format, data is changed in synchroniza tion with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the dat a communication direction can be switched by the specification of bit 1 (dir0) of serial oper ation mode specification register 0 (csima0). figure 17-11. format of transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 395 (c) switching msb/lsb as start bit figure 17-12 shows the configuration of serial i/o shi ft register 0 (sioa0) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. switching msb/lsb as the start bit can be specif ied using bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-12. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sia0 shift register 0 (sioa0) read/write gate soa0 scka0 dq soa0 latch start bit switching is realized by switching the bit or der for data written to sioa0. the sioa0 shift order remains unchanged. thus, switching between msb-first and lsb-first mu st be performed before wr iting data to the shift register. (d) communication start serial communication is st arted by setting communication data to se rial i/o shift register 0 (sioa0) when the following two conditions are satisfied. ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 396 17.4.3 3-wire serial i/o mode with au tomatic transmit/receive function up to 32 bytes of data can be transmi tted/received without using software in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is set to 1. after comm unication is started, only data of the set number of bytes stored in ram in advance can be transm itted, and only data of the set number of bytes can be received and stored in ram. in addition, to transmit/receive data continuously, handshake signals (stb0 and busy0) generated by hardware are supported. therefore, connec tion to peripheral lsis such as osd (on screen display) lsis and lcd controller/drivers can be easily realized. (1) registers used  serial operation mode specif ication register 0 (csima0)  serial status register 0 (csis0)  serial trigger register 0 (csit0)  divisor selection register 0 (brgca0)  automatic data transfer address point specification register 0 (adtp0)  automatic data transfer interval specification register 0 (adti0)  port mode register 14 (pm14)  port register 14 (p14) the relationship between the register settings and pins is shown below.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 397 table 17-4. relationship between register settings and pins csiae0 ate0 master0 stbe0 busye0 erre0 pm143 p143 pm144 p144 pm142 p142 pm145 p145 pm141 p141 serial i/o shift register 0 operation serial clock counter operation control 0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 398 (2) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fa00h of buffer ram (up to fa1fh at maximum). the transmit data should be in the or der from lower address to higher address. <2> set the automatic data transfer address point spec ification register 0 (adtp0) to the value obtained by subtracting 1 from the num ber of transmit data bytes. (b) setting example of automatic transmission/reception mode <1> set bit 7 (csiae0) and bit 6 (ate0) of serial operat ion mode specification register 0 (csima0) to 1. <2> set bit 2 (rxea0) and bit 3 (txea0) of csima0 to 1. <3> set a data transfer interval in automatic data transfer interval specification register 0 (adti0). <4> set bit 0 (atsta0) of serial trigger register 0 (csit0) to 1. caution take relationship with the other part y of communication when setting the port mode register and port register. the following operations are automatically carried out when (a) and (b) are carried out. ? ? ? ? ? ? ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 399 at this time, an interrupt request signal (intacsi ) is generated except when the csiae0 bit = 0. if a transfer is terminated in the middle, transfer star ting from the remaining data is not possible. read automatic data transfer address count register 0 (adt c0) to confirm how much of the data has already been transferred and re-execute transfer by performing (a) and (b) in (2) automatic transmit/receive data setting . in addition, when busy control and strobe control are not performed, the busy0/buz/intp7/p141 and stb0/p145 pins can be used as ordinary i/o port pins. figure 17-13 shows the operation timing in automat ic transmission/reception mode and figure 17-14 shows the operation flowchart. figure 17-15 shows t he operation of internal buffer ram when 6 bytes of data are transmitted/received. figure 17-13. automatic transmissi on/reception mode operation timings scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in th e automatic transmission/r eception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer ram after 1- byte transmission/reception, an in terval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the interval is depende nt upon the value of automatic data transfer interval specificati on register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status regi ster 0 (csis0) (see (5) automatic transmit/receive interval time). 2. if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the inte rval time specified by automatic data transfer interval specifi cation register 0 (adti0) may be extended. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 400 figure 17-14. automatic transm ission/reception mode flowchart start write transmit data in internal buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the automatic transmission/reception mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission/reception operation write receive data from sioa0 to internal buffer ram adtp0 = adtc0 no tsf0 = 0 no end yes yes increment pointer value software execution hardware execution software execution adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 401 in 6-byte transmission/reception (atm0 = 0, rxea0 = 1, txea0 = 1) in automa tic transmission/reception mode, internal buffer ram operates as follows. (i) starting transmission/recep tion (see figure 17-15 (a).) when bit 0 (atsta0) of serial trigger register 0 (csi t0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0. when trans mission of the first byte is completed, receive data 1 (r1) is transferred from sioa0 to the bu ffer ram, and automatic data transfer address count register 0 (adtc0) is incremented. then transmit data 2 (t2) is tr ansferred from the internal buffer ram to sioa0. (ii) 4th byte transmission/recep tion point (see figure 17-15 (b).) transmission/reception of the third byte is complete d, and transmit data 4 (t4) is transferred from the internal buffer ram to sioa0. when transmission of t he fourth byte is completed, the receive data 4 (r4) is transferred from sioa0 to the internal buffer ram, and adtc0 is incremented. (iii) completion of transmission/ reception (see figure 17-15 (c).) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sioa0 to the internal buffer ram, and the interrupt request flag (acsiif) is set (intacsi generation). bit 0 (tsf0) of serial status r egister 0 (csis0) is cleared. figure 17-15. internal buffer ram operat ion in 6-byte transmission/reception (in automatic transmissi on/reception mode) (1/2) (a) starting transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h receive data 1 (r1) sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 402 figure 17-15. internal buffer ram operat ion in 6-byte transmission/reception (in automatic transmissi on/reception mode) (2/2) (b) 4th byte transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) fa1fh fa05h fa00h receive data 4 (r4) sioa0 0 acsiif 3 adtc0 +1 5 adtp0 (c) completion of transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) fa1fh fa05h fa00h sioa0 1 acsiif 5 adtc0 5 adtp0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 403 (b) automatic transmission mode in this mode, the specified number of 8-bit unit data is transmitted. serial communication is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), and bit 3 (txea0) of serial operation mode s pecification register 0 (csima0) are set to 1. when the final byte has been transmitted, an interrupt request flag (acsiif) is set. the termination of automatic transmission and reception can also be jud ged by bit 0 (tsf0) of serial status register 0 (csis0). if a receive operation, busy control and strobe control are not executed, the sia0/p143, busy0/buz/intp7/p141, and stb0/p145 pins can be used as normal i/o port pins. figure 17-16 shows the automatic transmission mode operation timing, and figure 17-17 shows the operation flowchart. figure 17-18 shows the operation of the internal buffer ram when 6 bytes of data are transmitted. figure 17-16. automatic transm ission mode operation timing scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 interval cautions 1. because, in the automatic transmission mode, th e automatic transmit/receive function reads data from the internal bu ffer ram after 1-byte transmission, an interval is inserted until the next transmissi on. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer inte rval specification register 0 (adti0) and the set values of bits 5 and 4 (stbe0, busye0) of serial stat us register 0 (csis0) (see (5) automatic transmit/receive interval time). 2. if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the inte rval time specified by automatic data transfer interval specifi cation register 0 (adti0) may be extended. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 404 figure 17-17. automatic tr ansmission mode flowchart start write transmit data in internal buffer ram set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the automatic transmission mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no tsf0 = 0 no end yes yes increment pointer value software execution hardware execution software execution adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 405 in 6-byte transmission (atm0 = 0, rxea0 = 0, txea0 = 1, ate0 = 1) in automatic transmission mode, internal buffer ram operates as follows. (i) starting transmission (see figure 17-18 (a).) when bit 0 (atsta0) of serial trigger register 0 (csi t0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0. when transmi ssion of the first byte is completed, automatic data transfer address count register 0 (adtc0) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. (ii) 4th byte transmission point (see figure 17-18 (b).) transmission of the third byte is completed, and tr ansmit data 4 (t4) is transferred from the internal buffer ram to sioa0. when transmission of the f ourth byte is completed, adtc0 is incremented. (iii) completion of transmi ssion (see figure 17-18 (c).) when transmission of the sixth byte is completed, the interrupt requ est flag (acsiif) is set (intacsi generation). bit 0 (tsf0) of serial status register 0 (csis0) is cleared. figure 17-18. internal buffer ram operation in 6-byte transmission (in automatic transmission mode) (1/2) (a) starting transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 406 figure 17-18. internal buffer ram operation in 6-byte transmission (in automatic transmission mode) (2/2) (b) 4th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 3 adtc0 +1 5 adtp0 (c) completion of transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 1 acsiif 5 adtc0 5 adtp0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 407 (c) repeat transmission mode in this mode, data stored in the internal buffer ram is transmitted repeatedly. serial communication is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), bit 5 (atm0), and bit 3 (txea0) of serial operat ion mode specification register 0 (csima0) are set to 1. unlike the basic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (acsiif) is not set, automatic data transfe r address count register 0 (adtc0) is reset to 0, and the internal buffer ram contents are transmitted again. when a reception operation, busy control and stro be control are not performed, the sia0/p143, busy0/buz/intp7/p141, and st b0/p145 pins can be used as ordinary i/o port pins. the repeat transmission mode operation timing is shown in figure 17-19, and the operation flowchart in figure 17-20. figure 17-21 shows t he operation of the internal bu ffer ram when 6 bytes of data are transmitted in the repeat transmission mode. figure 17-19. repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 scka0 soa0 cautions 1. because, in the re peat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the inte rval is included in the period up to the next transmission. as the buffer ram re ad is performed at the same time as cpu processing, the interval is dependent upon au tomatic data transfer interval specification register 0 (adt i0) and the set values of bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0) (see (5) automatic transmit/recei ve interval time). 2. if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the inte rval time specified by automatic data transfer interval specifi cation register 0 (adti0) may be extended.
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 408 figure 17-20. repeat transmission mode flowchart start write transmit data in internal buffer ram set adtp0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes set the repeat transmission mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no yes increment pointer value software execution hardware execution reset adtc0 to 0 adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 409 in 6-byte transmission (atm0 = 1, rxea0 = 0, txea0 = 1, ate0 = 1) in re peat transmission mode, internal buffer ram operates as follows. (i) starting transmission (see figure 17-21 (a).) when bit 0 (atsta0) of serial trigger register 0 (csi t0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0. when transmi ssion of the first byte is completed, automatic data transfer address count register 0 (adtc0) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. (ii) upon completion of transmission of 6 bytes (see figure 17-21 (b).) when transmission of the sixth byte is completed, the interrupt request flag (acsiif) is not set. adtc0 is reset to 0. (iii) 7th byte transmission point (see figure 17-21 (c).) transmit data 1 (t1) is transferred from the internal buffer ram to sioa0 again. when transmission of the first byte is completed, adtc0 is increm ented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioa0. figure 17-21. internal buffer ram operation in 6-byte transmission (in repeat transmission mode) (1/2) (a) starting transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 410 figure 17-21. internal buffer ram operation in 6-byte transmission (in repeat transmission mode) (2/2) (b) upon completion of transmission of 6 bytes transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 5 adtc0 5 adtp0 (c) 7th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioa0 0 acsiif 0 adtc0 +1 5 adtp0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 411 (d) data format in the data format, data is changed in synchroniza tion with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the data trans fer direction can be switched by the specification of bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-22. format of csia0 transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 412 (e) automatic transmission/rece ption suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1. during 8-bit data communication, the transmission/reception is not suspended. it is suspended upon completion of 8-bit data communication. when suspended, bit 0 (tsf0) of serial status register 0 (csis0) is clea red to 0 after transfer of the 8th bit. cautions 1. if the halt inst ruction is executed during auto matic transmission/reception, communication is suspended and the halt mode is set if during 8-bit data communication. when the halt mode is cleared, automatic tr ansmission/reception is restarted from the suspended point. 2. when suspending automa tic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while tsf0 = 1. figure 17-23. automatic transmissi on/reception suspension and restart scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command atsta0 = 1 suspend atstp0 = 1 (suspend command) atstp0: bit 1 of serial trigger register 0 (csit0) atsta0: bit 0 of csit0
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 413 (4) synchronization control busy control and strobe control are functions used to synchronize transmission/reception between the master device and a slave device. by using these functions, a shift in bits bei ng transmitted or received can be detected. (a) busy control option busy control is a function to keep the serial transmissi on/reception by the master device waiting while the busy signal output by a slave device to the master is active. when using this busy control option, the fo llowing conditions must be satisfied. ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 414 figure 17-25. operation timing when busy c ontrol option is used (when busylv0 = 1) scka0 d7 soa0 sia0 acsiif d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 tsf0 busy input released busy input valid wait remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) when the busy signal becomes inactive, waiting is released. if the sampled busy signal is inactive, transmission/reception of the next 8-bit data is start ed at the falling edge of the next serial clock. because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. it takes 0.5 clock until data tran sfer is started after the busy signal was sampled. to accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clock. figure 17-26 shows the timing of the busy signal a nd releasing the waiting. this figure shows an example in which the busy signal is active as soon as transmission/recept ion has been started. figure 17-26. busy signal and wa it release (when busylv0 = 1) scka0 d7 soa0 sia0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 (active-high) 1.5 clocks (min.) busy input released busy input valid wait if made inactive immediately after sampled
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 415 (b) busy & strobe control option strobe control is a function used to synchronize data transmission/reception between the master and slave devices. the master device outputs the strobe signal from the stb0/p145 pin when 8-bit transmission/reception has been completed. by this signal, the slave device can determine the timing of the end of data transmission. therefor e, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmi ssion of the next byte is not affected by the bit shift. to use the strobe control opt ion, the following conditions must be satisfied: ? ?
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 416 (c) bit shift detection by busy signal during automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock sign al output by the master dev ice. unless the strobe control option is used at this time, the bit shift a ffects transmission of the next byte. in this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. a bit shift is detected by using the busy signal as follows: the slave outputs the busy signal after the risi ng of the eighth serial clock during data transmission/reception (to not keep trans mission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). the master samples the busy signal in synchronization with the falling edge of the serial clock if bit 2 (erre0) of serial status register 0 (csis0) is set to 1. if a bit shift does not occur, all the eight serial clocks that have been sample d are inactive. if the sampled serial cl ocks are active, it is assumed that a bit shift has occurred, error processing is executed (b y setting bit 1 (errf0) of serial status register 0 (csis0) to 1, and communication is suspended and an interrupt request signal (intacsi) is output). although communication is suspended after completion of 1-byte data communication, slave signal output, wait due to the busy signal, and wait due to the interval time specified by adti0 are not executed. if erre0 = 0, errf0 cannot become 1 even if a bit shift occurs. figure 17-28 shows the operation timing of the bi t shift detection function by the busy signal. remark the bit error function is valid both in the mast er mode and slave mode. the setting of erre0 is valid even when busye0 = 0. figure 17-28. operation timing of bit shift detection function by busy signal (when busylv0 = 0) scka0 (slave) d7 soa0 sia0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy0 acsiif csiae0 errf0 d7 d7 busy not detected error interrupt request generated error detected bit shift due to noise scka0 (master) acsiif: interrupt request flag csiae0: bit 7 of serial operation mode specification register 0 (csima0) errf0: bit 1 of serial status register 0 (csis0)
chapter 17 serial interface csia0 user?s manual u15947ej2v0ud 417 (5) automatic transmit/receive interval time when using the automatic transmit/receive function, t he read/write operations from/to the internal buffer ram are performed after transmitting/receiving one byte. th erefore, an interval is inserted before the next transmit/receive operation. since the read/write operations from/to the buffer ram are performed in parallel with the cpu processing when using the automatic transmit/receive function by th e internal clock, the interval depends on the value which is set in automatic data transfer interval spec ification register 0 (adti0) and bits 5 and 4 (stbe0, busye0) of serial status register 0 (csis0). when adti0 is cleared to 00h, an interval time bas ed on the to stbe0 and busye0 settings is generated. for example, when adti0 = 00h and stbe0 = busye0 = 1, an interval time of two clocks is generated. if an interval time of two clocks or more is set by adti0, the interval time set by adti0 is generated regardless of the stbe0 and busye0 settings. example interval time when busy signal is not generated <1> when stbe0 = 1, busye0 = 0: interval time of two serial clocks is generated <2> when stbe0 = 0, busye0 = 1: interv al time of one serial clock is generated <3> when stbe0 = 1, busye0 = 1: interval time of two serial clocks is generated figure 17-29. automatic tran smit/receive interval time scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval acsiif: interrupt request flag
user?s manual u15947ej2v0ud 418 chapter 18 multiplier/divider 18.1 functions of multiplier/divider the multiplier/divider has the following functions. ? ?
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 419 figure 18-1. block diagra m of multiplier/divider internal bus cpu clock start clear 17-bit adder controller multiplication/division data register b0 (mdb0 (mdb0h+mdb0l) remainder data register 0 (sdr0 (sdr0h+sdr0l) 6-bit counter dmusel0 multiplier/divider control register 0 (dmuc0) controller multiplication/division data register a0 (mda0h (mda0hh + mda0hl) + mda0l (mda0lh + mda0ll)) controller dmue mda000 intdmu
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 420 (1) remainder data register 0 (sdr0) sdr0 is a 16-bit register that stores a remainder. th is register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. this register can be read by an 8-bit or 16-bit memory manipulation instruction. reset input clears this register to 0000h. figure 18-2. format of remainder data register 0 (sdr0) address: ff60h, ff61h after reset: 0000h r symbol ff61h (sdr0h) ff60h (sdr0l) sdr0 sdr 015 sdr 014 sdr 013 sdr 012 sdr 011 sdr 010 sdr 009 sdr 008 sdr 007 sdr 006 sdr 005 sdr 004 sdr 003 sdr 002 sdr 001 sdr 000 cautions 1. the value read from sdr0 duri ng operation processing (while bit 7 (dmue) of multiplier/divider control register 0 (dmuc0) is 1) is not guaranteed. 2. sdr0 is reset when the operation is started (when dmue is set to 1).
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 421 (2) multiplication/division data register a0 (mda0h, mda0l) mda0 is a 32-bit register that sets a 16-bit multiplier a in the multiplication mode and a 32-bit dividend in the division mode, and stores the 32-bit result of the oper ation (higher 16 bits: mda0h, lower 16 bits: mda0l). figure 18-3. format of mult iplication/division data regi ster a0 (mda0h, mda0l) address: ff62h, ff63h, ff64h, ff65h after reset: 0000h, 0000h r/w symbol ff65h (mda0hh) ff64h (mda0hl) mda0h mda 031 mda 030 mda 029 mda 028 mda 027 mda 026 mda 025 mda 024 mda 023 mda 022 mda 021 mda 020 mda 019 mda 018 mda 017 mda 016 symbol ff63h (mda0lh) ff62h (mda0ll) mda0l mda 015 mda 014 mda 013 mda 012 mda 011 mda 010 mda 009 mda 008 mda 007 mda 006 mda 005 mda 004 mda 003 mda 002 mda 001 mda 000 cautions 1. mda0h is cleared to 0 when an operation is starte d in the multiplication mode (when multiplier/divider control regist er 0 (dmuc0) is set to 81h). 2. do not change the value of mda0 duri ng operation processing (whi le bit 7 (dmue) of multiplier/divider control regi ster 0 (dmuc0) is 1). even in this case, the operation is executed, but the result is undefined. 3. the value read from mda0 during oper ation processing (while dmue is 1) is not guaranteed.
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 422 the functions of mda0 when an operation is executed are shown in the table below. table 18-2. functions of mda0 during operation execution dmusel0 operation mode setting operation result 0 division mode di vidend division result (quotient) 1 multiplication mode higher 16 bits: 0, lower 16 bits: multiplier a multiplication result (product) the register configuration differs between when multiplication is executed and when division is executed, as follows. ? ?
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 423 18.3 register controlling multiplier/divider the multiplier/divider is controlled by mult iplier/divider control register 0 (dmuc0). (1) multiplier/divider c ontrol register 0 (dmuc0) dmuc0 is an 8-bit register that controls the operation of the multiplier/divider. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 18-5. format of multiplier/divider control register 0 (dmuc0) dmue dmuc0 0 0 0 0 0 0 dmusel0 stops operation starts operation dmue note 0 1 operation start/stop division mode multiplication mode dmusel0 0 1 operation mode (multiplication/division) selection address: ff68h after reset: 00h r/w symbol 4 3 2 1 0 6 <7> 5 note when dmue is set to 1, the operati on is started. dmue is automatically cleared to 0 after the operation is complete. cautions 1. if dmue is cleared to 0 during ope ration processing (when dmue is 1), the operation result is not guaranteed. if the operation is comple ted while the clearing instruction is being executed, the operation result is guaranteed, provided that the interrupt flag is set. 2. do not change the value of dmusel0 during operation processing (while dmue is 1). if it is changed, undefined operation resu lts are stored in multiplicati on/division data register a0 (mda0) and remainder data register 0 (sdr0). 3. if dmue is cleared to 0 during opera tion processing (while dmue is 1), the operation processing is stopped. to execute the operati on again, set multiplication/division data register a0 (mda0), multiplication/division data register b0 (mdb0), and multiplier/divider control register 0 (dmuc0), and star t the operation (by setting dmue to 1).
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 424 18.4 operations of multiplier/divider 18.4.1 multiplication operation ? ? ? ?
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 425 figure 18-6. timing chart of multiplication operation (00dah
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 426 18.4.2 division operation ? ? ? ?
chapter 18 multiplier/divider user?s manual u15947ej2v0ud 427 figure 18-7. timing chart of division operation (dcba2586h
user?s manual u15947ej2v0ud 428 chapter 19 interrupt functions 19.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrup ts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to its predetermined priority (see table 19-1 ). a standby release signal is generated a nd stop and halt modes are released. nine external interrupt requests and 20 (17 in the
chapter 19 interrupt functions user?s manual u15947ej2v0ud 429 table 19-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 end of csi10 communication/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and crh1 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and crh0 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 16 intad end of a/d conversion 0024h 17 intsr0 end of uart0 reception or reception error generation 0026h 18 intwti watch timer referenc e time interval signal 0028h maskable 19 inttm51 match between tm51 and cr51 (when compare register is specified) internal 002ah (a) notes 1. the default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 28 is the lowest. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 19-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 0.
chapter 19 interrupt functions user?s manual u15947ej2v0ud 430 table 19-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 20 intkr key interrupt detection external 002ch (c) 21 intwt watch timer overflow internal 002eh (a) 22 intp6 0030h 23 intp7 pin input edge detection external 0032h (b) 24 intdmu end of multiply/divide operation 0034h 25 intcsi11 note 3 end of csi11 communication 0036h 26 inttm001 note 3 match between tm01 and cr001 (when compare register is specified), ti011 pin valid edge detection (when capture register is specified) 0038h 27 inttm011 note 3 match between tm01 and cr011 (when compare register is specified), ti001 pin valid edge detection (when capture register is specified) 003ah maskable 28 intacsi end of csia0 communication internal 003ch (a) software ? ? ? ? ?
chapter 19 interrupt functions user?s manual u15947ej2v0ud 431 figure 19-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp7) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag
chapter 19 interrupt functions user?s manual u15947ej2v0ud 432 figure 19-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal key interrupt detector 1 when krmn = 1 (n = 0 to 7) (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register 19.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? ? ? ? ? ?
chapter 19 interrupt functions user?s manual u15947ej2v0ud 433 table 19-2. flags corresponding to interrupt request sources interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 dualif0 note 1 dualmk0 note 2 dualpr0 note 2 intst0 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 intad adif if1l admk mk1l adpr pr1l intsr0 srif0 srmk0 srpr0 intwti wtiif wtimk wtipr inttm51 tmif51 tmmk51 tmpr51 intkr krif krmk krpr intwt wtif wtmk wtpr intp6 pif6 pmk6 ppr6 intp7 pif7 pmk7 ppr7 intdmu dmuif if1h dmumk mk1h dmupr pr1h intcsi11 note 3 csiif11 note 3 csimk11 note 3 csipr11 note 3 inttm001 note 3 tmif001 note 3 tmmk001 note 3 tmpr001 note 3 inttm011 note 3 tmif011 note 3 tmmk011 note 3 tmpr011 note 3 intacsi acsiif acsimk acsipr notes 1. if either of the two types of interrupt s ources is generated, these flags are set (1). 2. both types of interrupt sources are supported. 3.
chapter 19 interrupt functions user?s manual u15947ej2v0ud 434 (1) interrupt request flag regi sters (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset input. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruct ion. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are set by a 16-bit memory manipulation instruction. reset input clears these registers to 00h. figure 19-2. format of interrupt request fl ag registers (if0l, if0h, if1l, if1h) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 dualif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l pif7 pif6 wtif krif tmif51 wtiif srif0 adif address: ffe3h after reset: 00h r/w symbol 7 6 5 <4> <3> <2> <1> <0> if1h 0 note 1 0 note 1 0 note 1 acsiif tmif011 note 2 tmif001 note 2 csiif11 note 2 dmuif xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. be sure to clear bits 5 to 7 of if1h to 0. 2.
chapter 19 interrupt functions user?s manual u15947ej2v0ud 435 (2) interrupt mask flag regist ers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8- bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit registers mk0 and mk1, they are set by a 16-bit memory manipulation instruction. reset input sets mk0l, mk0h, and mk1l to ffh and mk1h to dfh. figure 19-3. format of interrupt mask fl ag registers (mk0l, mk0h, mk1l, mk1h) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 dualmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l pmk7 pmk6 wtmk krmk tmmk51 wtimk srmk0 admk address: ffe7h after reset: dfh r/w symbol 7 6 5 <4> <3> <2> <1> <0> mk1h 1 note 1 1 note 1 0 note 1 acsimk tmmk011 note 2 tmmk001 note 2 csimk11 note 2 dmumk xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. be sure to set bits 6 and 7 of mk1h to 1 and clear bit 5 to 0. 2.
chapter 19 interrupt functions user?s manual u15947ej2v0ud 436 (3) priority specification flag re gisters (pr0l, pr0h, pr1l, pr1h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bi t memory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-4. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 dualpro stpr6 srpr6 address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l ppr7 ppr6 wtpr krpr tmpr51 wtipr srpr0 adpr address: ffebh after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr1h 1 note 1 1 note 1 1 note 1 acsipr tmpr011 note 2 tmpr001 note 2 csipr11 note 2 dmupr xxprx priority level selection 0 high priority level 1 low priority level notes 1. be sure to set bits 5 to 7 of pr1h to 1. 2.
chapter 19 interrupt functions user?s manual u15947ej2v0ud 437 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp7. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 19-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp egp7 epg6 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn egn7 egn6 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 7) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 19-3 shows the ports corresponding to egpn and egnn. table 19-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120 intp0 egp1 egn1 p30 intp1 egp2 egn2 p31 intp2 egp3 egn3 p32 intp3 egp4 egn4 p33 intp4 egp5 egn5 p16 intp5 egp6 egn6 p140 intp6 egp7 egn7 p141 intp7 caution select the port mode by clearing egpn and egnn to 0 because an edge may be detected when the external interrupt function is switched to the port function. remark n = 0 to 7
chapter 19 interrupt functions user?s manual u15947ej2v0ud 438 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1
chapter 19 interrupt functions user?s manual u15947ej2v0ud 439 19.4 interrupt servicing operations 19.4.1 maskable interrupt request acknowledgement a maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled stat e (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 19-4 below. for the interrupt request acknowledgment timing, see figures 19-8 and 19-9 . table 19-4. time from ge neration of maskable interrupt request until servicing minimum time maximum time note when
chapter 19 interrupt functions user?s manual u15947ej2v0ud 440 figure 19-7. interrupt request acknowledgment processing algorithm start
chapter 19 interrupt functions user?s manual u15947ej2v0ud 441 figure 19-8. interrupt request ac knowledgment timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing
chapter 19 interrupt functions user?s manual u15947ej2v0ud 442 19.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the inte rrupt request acknowledgment enabled state is selected (ie = 1). also, when an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt current ly being serviced is generated during interr upt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pe nding. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execut ion of one main processing instruction execution. table 19-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 19-10 shows multiple interrupt servicing examples. table 19-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0
chapter 19 interrupt functions user?s manual u15947ej2v0ud 443 figure 19-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled
chapter 19 interrupt functions user?s manual u15947ej2v0ud 444 figure 19-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled
chapter 19 interrupt functions user?s manual u15947ej2v0ud 445 19.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for t hem while another instruction is being executed, request acknowledgment is held pending until the end of execution of the ne xt instruction. these instructions (interrupt request hol d instructions) are listed below. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
user?s manual u15947ej2v0ud 446 chapter 20 key interrupt function 20.1 functions of key interrupt a key interrupt (intkr) can be generated by setting the key return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 20-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 20.2 configuration of key interrupt the key interrupt consists of the following hardware. table 20-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 20-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 edge detector
chapter 20 key interrupt function user?s manual u15947ej2v0ud 447 20.3 register controlling key interrupt (1) key return mode register (krm) this register controls the krm0 to krm7 bits using the kr0 to kr7 signals, respectively. this register is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 20-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 cautions 1. if any of the krm0 to krm7 bits used is set to 1, set bits 0 to 7 (pu70 to pu77) of the corresponding pull-up resistor register 7 (pu7) to 1. 2. if krm is changed, the interrupt request fl ag may be set. therefo re, disable interrupts and then change the krm register. clear the in terrupt request flag and enable interrupts. 3. the bits not used in the key inte rrupt mode can be used as normal ports.
user?s manual u15947ej2v0ud 448 chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function table 21-1. relationship between operat ion clocks in each operation status x1 oscillator ring-osc oscillator prescaler clock supplied to peripherals note 2 status operation mode mstop = 0 mcc = 0 mstop = 1 mcc = 1 note 1 rstop = 0 rstop = 1 subsystem clock oscillator cpu clock after release mcm0 = 0 mcm0 = 1 reset stopped ring-osc stopped stop stopped note 3 stopped halt oscillating stopped oscillating oscillating stopped oscillating note 4 ring-osc x1 notes 1. when ?cannot be stopped? is select ed for ring-osc by a mask option. 2. when ?can be stopped by software? is selected for ring-osc by a mask option. 3. operates using the cpu clock at stop instruction execution. 4. operates using the cpu clock at halt instruction execution. caution the rstop setting is valid only when ?can be stopped by software? is set for ring-osc by a mask option. remark mstop: bit 7 of the main osc control register (moc) mcc: bit 7 of the processor clock control register (pcc) rstop: bit 0 of the ring-osc mode register (rcm) mcm0: bit 0 of the main clock mode register (mcm) the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution sets the ha lt mode. in the halt mode, the cpu operation clock is stopped. if the x1 oscillator, ring-osc oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the stop mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations.
chapter 21 standby function user?s manual u15947ej2v0ud 449 (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the x1 oscillator stops, stopping the whole system, thereby considerably r educing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. stop mode can be used only when cp u is operating on the x1 input clock or ring-osc clock. halt mode can be used when cpu is operating on the x1 input clock, ring-osc clock, or subsystem cl ock. however, when the stop instruction is executed during ring- osc clock operation, the x1 oscillator st ops, but ring-osc oscillator does not stop. 2. when shifting to the stop mode, be sure to stop the peri pheral hardware operation before executing stop instruction. 3. the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) of the a/d converter mode register (adm) to 0 to stop the a/d conversi on operation, and then execute the halt or stop instruction. 4. if the ring-osc oscillator is operating before the stop mode is set, oscillation of the ring- osc clock cannot be stopped in the stop mode. however, when the ri ng-osc clock is used as the cpu clock, the cpu operation is stopped for 17/f r (s) after stop mode is released.
chapter 21 standby function user?s manual u15947ej2v0ud 450 21.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? ? ?
chapter 21 standby function user?s manual u15947ej2v0ud 451 (2) oscillation stabilization time select register (osts) this register is used to select the x1 oscillation stab ilization wait time when stop mode is released. the wait time set by osts is valid only after stop mode is released when the x1 input clock is selected as the cpu clock. after stop mode is released when the ring-osc clock is selected, check the oscillation stabilization time using ostc. osts can be set by an 8-bit memory manipulation instruction. reset input sets osts to 05h. figure 21-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection 0 0 1 2 11 /f x (204.8 ?
chapter 21 standby function user?s manual u15947ej2v0ud 452 21.2 standby function operation 21.2.1 halt mode (1) halt mode the halt mode is set by executing the halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the x1 input clo ck, ring-osc clock, or subsystem clock. the operating statuses in t he halt mode are shown below. table 21-2. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on x1 input clock when halt instruction is executed while cpu is operating on ring-osc clock when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when x1 input clock oscillation continues when x1 input clock oscillation stopped halt mode setting item when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used system clock clock supply to the cpu is stopped. cpu operation stopped port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 operable operation not guaranteed 16-bit timer/event counter 01 note 2 operable operation not guaranteed 8-bit timer/event counter 50 operable operati on not guaranteed when count clock other than ti50 is selected 8-bit timer/event counter 51 operable operati on not guaranteed when count clock other than ti51 is selected 8-bit timer h0 operable operation not guaranteed when count clock other than tm50 output is selected during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operation not guaranteed when count clock other than f r /2 7 is selected watch timer operable operable note 3 operable operable note 3 operable note 4 operation not guaranteed operable note 4 operation not guaranteed ring-osc cannot be stopped note 5 operable ?
chapter 21 standby function user?s manual u15947ej2v0ud 453 table 21-2. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock when x1 input clock oscillation continues when x1 input clock oscillation stopped halt mode setting item when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when ring-osc oscillation continues when ring-osc oscillation stopped note 1 system clock clock supply to the cpu is stopped. cpu operation stopped port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 operable operation stopped 16-bit timer/event counter 01 note 2 operable operation stopped 8-bit timer/event counter 50 operable operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable operable onl y when ti51 is select ed as the count clock 8-bit timer h0 operable operable only when tm50 output is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable operable only when the x1 input clock is selected as the count clock operable only when f r /2 7 is selected as the count clock operation stopped watch timer operable operable only wh en subsystem clo ck is selected ring-osc cannot be stopped note 3 operable ? ?
chapter 21 standby function user?s manual u15947ej2v0ud 454 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgement is enabled, vectored interrupt servicin g is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 21-3. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation x1 input clock, ring-osc clock, or subsystem clock status of cpu standby release signal interrupt request remarks 1. the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows:  when vectored interrupt servicing is carried out: 8 or 9 clocks  when vectored interrupt servicing is not carried out: 2 or 3 clocks
chapter 21 standby function user?s manual u15947ej2v0ud 455 (b) release by reset input when the reset signal is input, halt mode is rele ased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 21-4. halt mode release by reset input (1/2) (1) when x1 input clock is used as cpu clock halt instruction reset signal x1 input clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) (2) when ring-osc clo ck is used as cpu clock halt instruction reset signal ring-osc clock operating mode halt mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency
chapter 21 standby function user?s manual u15947ej2v0ud 456 figure 21-4. halt mode release by reset input (2/2) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock operating mode halt mode reset period operation stopped operating mode oscillates status of cpu (ring-osc clock) (17/f r ) subsystem clock remark f r : ring-osc clock oscillation frequency table 21-3. operation in response to interrupt request in halt mode release source mk ? ?
chapter 21 standby function user?s manual u15947ej2v0ud 457 21.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing the stop instruction, and it can be set when the cpu clock before the setting was the x1 input clock or ring-osc clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. table 21-4. operating statuses in stop mode when stop instruction is executed while cpu is operating on x1 input clock when ring-osc oscillation continues when ring-osc oscillation stopped note 1 when stop instruction is executed while cpu is operating on ring- osc clock stop mode setting item when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used when subsystem clock used when subsystem clock not used system clock only x1 oscillator oscillation is stopped. clock supply to the cpu is stopped. cpu operation stopped port (latch) status before st op mode was set is retained 16-bit timer/event counter 00 operation stopped 16-bit timer/event counter 01 note 2 operation stopped 8-bit timer/event counter 50 operable only when ti50 is selected as the count clock 8-bit timer/event counter 51 operable only when ti51 is selected as the count clock 8-bit timer h0 operable only when tm50 output is selected as the count clock during 8-bit timer/event counter 50 operation 8-bit timer h1 operable note 3 operation stopped operable note 3 watch timer operable note 4 operation stopped operable note 4 operation stopped operable note 4 operation stopped ring-osc cannot be stopped note 5 operable ?
chapter 21 standby function user?s manual u15947ej2v0ud 458 (2) stop mode release figure 21-5. operation timing wh en stop mode is released ring-osc clock is selected as cpu clock when stop instruction is executed ring-osc clock x1 input clock x1 input clock is selected as cpu clock when stop instruction is executed stop mode release stop mode operation stopped (17/f r ) clock switched by software ring-osc clock x1 input clock halt status (oscillation stabilization time set by osts) x1 input clock the stop mode can be released by the following two sources.
chapter 21 standby function user?s manual u15947ej2v0ud 459 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 21-6. stop mode release by interrupt request generation (1) when x1 input clock is used as cpu clock operating mode operating mode oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped x1 input clock status of cpu oscillation stabilization time (set by osts) (x1 input clock) (x1 input clock) (2) when ring-osc clo ck is used as cpu clock operating mode operating mode oscillates stop instruction stop mode standby release signal ring-osc clock status of cpu (ring-osc clock) operation stopped (17/f r ) (ring-osc clock) remarks 1. the broken lines indicate the case when the in terrupt request that has released the standby mode is acknowledged. 2. f r : ring-osc clock oscillation frequency
chapter 21 standby function user?s manual u15947ej2v0ud 460 (b) release by reset input when the reset signal is input, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 21-7. stop mode release by reset input (1) when x1 input clock is used as cpu clock stop instruction reset signal x1 input clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (x1 input clock) oscillation stabilization time (2 11 /f xp to 2 16 /f xp ) (ring-osc clock) (17/f r ) oscillation stopped (2) when ring-osc clo ck is used as cpu clock stop instruction reset signal ring-osc clock operating mode stop mode reset period operation stopped operating mode oscillates oscillation stopped oscillates status of cpu (ring-osc clock) (17/f r ) (ring-osc clock) remarks 1. f xp : x1 input clock oscillation frequency 2. f r : ring-osc clock oscillation frequency table 21-5. operation in response to interrupt request in stop mode release source mk ? ?
user?s manual u15947ej2v0ud 461 chapter 22 reset function the following five operations are available to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by cl ock monitor x1 clock oscillation stop detection (4) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (5) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is input. a reset is applied when a low level is input to the reset pin, th e watchdog timer overflow s, x1 clock oscillation stop is detected by the clock monitor, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in table 22-1. each pin is high impedan ce during reset input or during the oscillation stabilization time just after reset release, except for p130, which is low-level output. when a high level is input to the reset pin, the reset is released and progr am execution starts using the ring- osc clock after the cpu clock operation has stopped for 17/f r (s). a reset generated by the watchdog timer and clock monitor sources is automatically released after th e reset, and program executi on starts using the ring-osc clock after the cpu clock operation has stopped for 17/f r (s) (see figures 22-2 to 22-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after the reset, and program execution starts using the ring-osc clock afte r the cpu clock operation has stopped for 17/f r (s) (see chapter 24 power-on-clear circuit and chapter 25 low-voltage detector ). cautions 1. for an external reset, input a low level for 10
chapter 22 reset function user?s manual u15947ej2v0ud 462 figure 22-1. block di agram of reset function clmrf lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal clock monitor reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal reset signal to lvim/lvis register clear set set clear clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register
chapter 22 reset function user?s manual u15947ej2v0ud 463 figure 22-2. timing of reset by reset input delay delay hi-z note normal operation cpu clock reset period (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) reset internal reset signal port pin x1 input clock ring-osc clock note the port pins become high impedance, except for p130, which is set to low-level output. figure 22-3. timing of reset du e to watchdog timer overflow hi-z note normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal port pin operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 input clock ring-osc clock note the port pins become high impedance, except for p130, which is set to low-level output. caution a watchdog timer internal reset resets the watchdog timer.
chapter 22 reset function user?s manual u15947ej2v0ud 464 figure 22-4. timing of reset in stop mode by reset input delay delay hi-z note normal operation cpu clock reset period (oscillation stop) reset internal reset signal port pin stop instruction execution stop status (oscillation stop) operation stop (17/f r ) normal operation (reset processing, ring-osc clock) x1 input clock ring-osc clock note the port pins become high impedance, except for p130, which is set to low-level output. remark for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 24 power- on-clear circuit and chapter 25 low-voltage detector .
chapter 22 reset function user?s manual u15947ej2v0ud 465 table 22-1. hardware statuses after reset acknowledgment (1/3) hardware status after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p0 to p7, p12 to p14) (output latches) 00h (undefined only for p2) port mode registers (pm0, pm1, pm3 to pm7, pm12, pm14) ffh pull-up resistor option registers (pu0, pu1, pu3 to pu7, pu12, pu14) 00h input switch control register (isc) 00h internal memory size switching register (ims) cfh internal expansion ram size sw itching register (ixs) 0ch memory expansion mode register (mem) 00h memory expansion wait setting register (mm) 10h processor clock control register (pcc) 00h ring-osc mode register (rcm) 00h main clock mode register (mcm) 00h main osc control register (moc) 00h oscillation stabilization time select register (osts) 05h oscillation stabilization time counter status register (ostc) 00h timer counters 00, 01 (tm00, tm01) 0000h capture/compare registers 000, 010, 001, 011 (cr000, cr010, cr001, cr011) 0000h mode control registers 00, 01 (tmc00, tmc01) 00h prescaler mode registers 00, 01 (prm00, prm01) 00h capture/compare control registers 00, 01 (crc00, crc01) 00h 16-bit timer/event counters 00, 01 note 3 timer output control registers 00, 01 (toc00, toc01) 00h timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) 00h timer clock selection regist ers 50, 51 (tcl50, tcl51) 00h 8-bit timer/event counters 50, 51 mode control registers 50, 51 (tmc50, tmc51) 00h compare registers 00, 10, 01, 11 (cmp00, cmp10, cmp01, cmp11) 00h mode registers (tmhmd0, tmhmd1) 00h 8-bit timers h0, h1 carrier control register 1 (tmcyc1) note 4 00h watch timer operation m ode register (wtm) 00h clock output/buzzer output controller clock output selection register (cks) 00h notes 1. during reset input or oscillation stabilization time wa it, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. 16-bit timer/event counter 01 is available only for the
chapter 22 reset function user?s manual u15947ej2v0ud 466 table 22-1. hardware statuses after reset acknowledgment (2/3) hardware status after reset acknowledgment mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result register (adcr) undefined mode register (adm) 00h analog input channel specification register (ads) 00h power-fail comparison mode register (pfm) 00h a/d converter power-fail comparison threshold register (pft) 00h receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface oper ation mode register 0 (asim0) 01h serial interface uart0 baud rate generator control register 0 (brgc0) 1fh receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmis sion status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh serial interface uart6 asynchronous serial interface control register 6 (asicl6) 16h transmit buffer registers 10, 11 (sotb10, sotb11) undefined serial i/o shift registers 10, 11 (sio10, sio11) undefined serial operation mode registers 10, 11 (csim10, csim11) 00h serial interfaces csi10, csi11 note serial clock selection register s 10, 11 (csic10, csic11) 00h shift register 0 (sioa0) 00h operation mode specification register 0 (csima0) 00h status register 0 (csis0) 00h trigger register 0 (csit0) 00h divisor selection register 0 (brgca0) 03h automatic data transfer address point specification register 0 (adtp0) 00h automatic data transfer interval specification register 0 (adti0) 00h serial interface csia0 automatic data transfer address count register 0 (adtc0) 00h remainder data register 0 (sdr0) 0000h multiplication/division data regi ster a0 (mda0h, mda0l) 0000h multiplication/division data register b0 (mdb0) 0000h multiplier/divider multiplier/divider control register 0 (dmuc0) 00h key interrupt key return mode register (krm) 00h clock monitor mode register (clm) 00h note serial interface csi11 is available only for the
chapter 22 reset function user?s manual u15947ej2v0ud 467 table 22-1. hardware statuses after reset acknowledgment (3/3) hardware status after reset acknowledgment reset function reset control flag register (resf) 00h note low-voltage detection register (lvim) 00h note low-voltage detector low-voltage detection level selection register (lvis) 00h note request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l (mk0l, mk0h, mk1l) ffh mask flag register 1h (mk1h) dfh priority specification flag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h note these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by clm reset by lvi resf see table 22-2 . lvim lvis cleared (00h) cleared (00h) cleared (00h) cleared (00h) held
chapter 22 reset function user?s manual u15947ej2v0ud 468 22.1 register for confirming reset source many internal reset generation sources exist in the 78k0/kf 1. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc ) circuit, and reading resf clear resf to 00h. figure 22-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 clmrf lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. clmrf internal reset req uest by clock monitor (clm) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 22-2. table 22-2. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by clm reset by lvi wdtrf set (1) held held clmrf held set (1) held lvirf cleared (0) cleared (0) held held set (1)
user?s manual u15947ej2v0ud 469 chapter 23 clock monitor 23.1 functions of clock monitor the clock monitor samples the x1 input clock using the on-chip ring-osc, and generates an internal reset signal when the x1 input clock is stopped. when a reset signal is generated by the clock monitor, bit 1 (clmrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 22 reset function . the clock monitor automatically stops under the following conditions. ? ? ? ?
chapter 23 clock monitor user?s manual u15947ej2v0ud 470 23.3 registers controlling clock monitor clock monitor is controlled by the clock monitor mode register (clm). (1) clock monitor mode register (clm) this register sets the operation mode of the clock monitor. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 23-2. format of clock monitor mode register (clm) 7 0 clme 0 1 symbol clm address: ffa9h after reset: 00h r/w 6 0 disables clock monitor operation enables clock monitor operation 5 0 4 0 3 0 enables/disables clock monitor operation 2 0 1 0 <0> clme cautions 1. once bit 0 (clme) is set to 1, it cannot be cleared to 0 except by re set input or the internal reset signal. 2. if the reset signal is generated by the clock monitor, clme is cleared to 0 and bit 1 (clmrf) of the reset control flag regi ster (resf) is set to 1.
chapter 23 clock monitor user?s manual u15947ej2v0ud 471 23.4 operation of clock monitor this section explains the functions of the clock monitor. the monitor star t and stop conditions are as follows. when bit 0 (clme) of the clock monitor mode r egister (clm) is set to operation enabled (1). ? ? ? ?
chapter 23 clock monitor user?s manual u15947ej2v0ud 472 figure 23-3. timing of clock monitor (1/4) (1) when internal reset is executed by oscillation stop of x1 input clock 4 clocks of ring-osc clock x1 input clock ring-osc clock internal reset signal clme clmrf (2) clock monitor status after reset input (clme = 1 is set after reset input and during x1 input clock oscillation stabilization time) cpu operation clock monitor status clme ring-osc clock x1 input clock reset oscillation stopped oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring waiting for end of oscillation stabilization time oscillation stopped 17 clocks set to 1 by software reset reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. even if clme is set to 1 by software during the oscillation stabilization time (reset value of osts register is 05h (2 16 /f xp )) of the x1 input clock, monitoring is not performed un til the oscillation stabilizat ion time of the x1 input clock ends. monitoring is automatically started at the end of the oscillation stabilization time.
chapter 23 clock monitor user?s manual u15947ej2v0ud 473 figure 23-3. timing of clock monitor (2/4) (3) clock monitor status after reset input (clme = 1 is set after reset input and at the e nd of x1 input clock oscillation stabilization time) cpu operation clock monitor status clme reset ring-osc clock x1 input clock reset oscillation stabilization time normal operation clock supply stopped normal operation (ring-osc clock) monitoring monitoring stopped monitoring 17 clocks set to 1 by software reset input clears bit 0 (clme) of the clock monitor mode register (clm) to 0 and stops the clock monitor operation. when clme is set to 1 by software at the end of the oscillation stabilization time (reset value of osts register is 05h (2 16 /f xp )) of the x1 input clock, monitoring is started. (4) clock monitor status a fter stop mode is released (clme = 1 is set when cpu clock operates on x1 input clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring clme ring-osc clock x1 input clock (cpu clock) cpu operation normal operation stop oscillation stabilization time normal operation oscillation stopped oscillation stabilization time (time set by osts register) when bit 0 (clme) of the clock monitor mode register (c lm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time.
chapter 23 clock monitor user?s manual u15947ej2v0ud 474 figure 23-3. timing of clock monitor (3/4) (5) clock monitor status a fter stop mode is released (clme = 1 is set when cpu clock operates on ri ng-osc clock and before entering stop mode) clock monitor status monitoring monitoring stopped monitoring stopped monitoring clme ring-osc clock (cpu clock) x1 input clock cpu operation normal operation 17 clocks clock supply stopped normal operation oscillation stopped oscillation stabilization time (time set by osts register) stop when bit 0 (clme) of the clock monitor mode register (c lm) is set to 1 before entering stop mode, monitoring automatically starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped in stop mode and during the oscillation stabilization time. (6) clock monitor status after x1 input clock oscillation is stopped by software clock monitor status clme mstop or mcc note ring-osc clock x1 input clock oscillation stabilization time (time set by osts register) normal operation (ring-osc clock or subsystem clock note ) monitoring monitoring stopped monitoring cpu operation monitoring stopped oscillation stopped when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before or while oscillation of the x1 input clock is stopped, monitoring automatical ly starts at the end of the x1 input clock oscillation stabilization time. monitoring is stopped when oscillation of the x1 input clo ck is stopped and during the osc illation stabilization time. note the register that controls oscillati on of the x1 input clock differs depen ding on the type of the clock supplied to the cpu. ? ?
chapter 23 clock monitor user?s manual u15947ej2v0ud 475 figure 23-3. timing of clock monitor (4/4) (7) clock monitor status after ring-osc clock oscillation is stopped by software ring-osc clock x1 input clock cpu operation normal operation (x1 input clock or subsystem clock) oscillation stopped rstop note clock monitor status monitoring monitoring stopped monitoring clme when bit 0 (clme) of the clock monitor mode register (clm) is set to 1 before or while oscillation of the ring-osc clock is stopped, monitoring automatically starts afte r the ring-osc clock is stopped. monitoring is stopped when oscillation of the ring-osc clock is stopped. note if it is specified by a mask option that ring-osc cannot be stopped, the setting of bit 0 (rstop) of the ring-osc mode register (rcm) is invalid. to set rsto p, be sure to confirm that bit 1 (mcs) of the main clock mode register (mcm) is 1.
user?s manual u15947ej2v0ud 476 chapter 24 power-on-clear circuit 24.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? ? ? ? ? ?
chapter 24 power-on-clear circuit user?s manual u15947ej2v0ud 477 24.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 24-1. figure 24-1. block diagram of power-on-clear circuit ?
chapter 24 power-on-clear circuit user?s manual u15947ej2v0ud 478 24.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a time r, and then initialize the ports. figure 24-3. example of software pr ocessing after release of reset (1/2) ?
chapter 24 power-on-clear circuit user?s manual u15947ej2v0ud 479 figure 24-3. example of software pr ocessing after release of reset (2/2) ?
user?s manual u15947ej2v0ud 480 chapter 25 low-voltage detector 25.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? ? ? ? ?
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 481 25.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? ?
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 482 figure 25-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd 2 0 3 0 <4> lvie 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h r/w note 1 lvion notes 2, 3 enables low-voltage detection operation 0 disables operation 1 enables operation lvie notes 2, 4, 5 specifies reference voltage generator 0 disables operation 1 enables operation lvimd note 2 low-voltage detection operation mode selection 0 generates interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 6 low-voltage detection flag 0 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. bit 0 is read-only. 2. lvion, lvie, and lvimd are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 3. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 4. if ?poc cannot be used? is selected by a mask opti on, wait for 2 ms or more by software from when lvie is set to 1 until lvion is set to 1. 5. if ?poc used? is selected by a mask option, se tting of lvie is invalid because the reference voltage generator in the lvi circuit always operates. 6. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. caution to stop lvi, follow either of the procedures below. ? ?
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 483 (2) low-voltage detection level selection register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. reset input clears lvis to 00h. figure 25-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 0 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h r/w lvis2 lvis1 lvis0 detection level 0 0 0 v lvi0 (4.3 v
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 484 25.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 2 to 0 (lvis2 to lvis0) of the low-voltage detection level selection register (lvis). <3> set bit 4 (lvie) of the low-voltage detection regist er (lvim) to 1 (enables reference voltage generator operation). <4> use software to instigate a wait of at least 2 ms. <5> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <6> use software to instigate a wait of at least 0.2 ms. <7> wait until it is checked that (supply voltage (v dd ) > detection voltage (v lvi )) by bit 0 (lvif) of lvim. <8> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). figure 25-4 shows the timing of the internal reset signal generated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <5>. 2. if ?poc used? is selected by a mask opt ion, procedures <3> and <4> are not required. 3. if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0, lvion to 0, and lvie to 0 in that order.
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 485 figure 25-4. timing of low-voltage dete ctor internal reset signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared not cleared not cleared cleared by software <2> <1> note 1 <5> <7> <8> time clear clear clear clear <3> <4> 2 ms or longer <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) lvimd flag (set by software) notes 1. the lvimk flag is set to ?1? by reset input. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag register (resf). for details of resf, see chapter 22 reset function . remark <1> to <8> in figure 25-4 above correspond to <1> to <8> in the description of ?when starting operation? in 25.4 (1) when used as reset .
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 486 (2) when used as interrupt ? ? ? ?
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 487 figure 25-5. timing of low-voltage detector interrupt signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) 2.7 v time lvif flag intlvi lviif flag internal reset signal <2> <1> note 1 <5> <7> <8> cleared by software <3> <4> 2 ms or longer <9> cleared by software <6> 0.2 ms or longer lvimk flag (set by software) lvie flag (set by software) lvion flag (set by software) note 2 note 2 notes 1. the lvimk flag is set to ?1? by reset input. 2. the lvif and lviif flags may be set (1). remark <1> to <9> in figure 25-5 above correspond to <1> to <9> in the description of ?when starting operation? in 25.4 (2) when used as interrupt .
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 488 25.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take action (2) below. in this system, take the following actions. (1) when used as reset after releasing the reset signal, wait for the supply voltage fluctuation pe riod of each system by means of a software counter that uses a time r, and then initialize the ports.
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 489 figure 25-6. example of software pr ocessing after release of reset (1/2) ?
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 490 figure 25-6. example of software pr ocessing after release of reset (2/2) ?
chapter 25 low-voltage detector user?s manual u15947ej2v0ud 491 (2) when used as interrupt check that ?supply voltage (v dd ) > detection voltage (v lvi )? in the servicing routine of the lvi interrupt by using bit 0 (lvif) of the low-voltage detection register (lvim). clear bit 0 (lviif) of interrupt request flag register 0l (if0l) to 0 and enable interrupts (ei). in a system where the supply voltage fluc tuation period is long in the vicinity of the lvi detection voltage, wait for the supply voltage fluctuation peri od, check that ?supply voltage (v dd ) > detection voltage (v lvi )? using the lvif flag, and then enable interrupts (ei).
user?s manual u15947ej2v0ud 492 chapter 26 regulator 26.1 outline of regulator the 78k0/kf1 includes a circuit to realize constant-voltage operation inside the device. to stabilize the regulator output voltage, connect the regc pin to v ss via a capacitor (1 ? ? ? ? ?
chapter 26 regulator user?s manual u15947ej2v0ud 493 figure 26-2. regc pin connection (a) when regc = v dd reg input voltage = 2.7 to 5.5 v voltage supply to oscillator/internal logic = 2.7 to 5.5 v v dd regc (b) when connecting regc pin to v ss via a capacitor reg input voltage = 4.0 to 5.5 v voltage supply to oscillator/internal logic = 3.5 v v dd regc 1 f (recommended)
user?s manual u15947ej2v0ud 494 chapter 27 mask options mask rom versions are provided with the following mask options. 1. power-on-clear (poc) circuit ? ? ? ? ? ?
user?s manual u15947ej2v0ud 495 chapter 28
chapter 28 cfh caution when using a mask rom vers ion, be sure to set the value indicated in table 28-2 to ims.
chapter 28 0ah caution when using a mask rom vers ion, be sure to set the value indicated in table 28-3 to ixs.
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chapter 28 pd78f0148 user?s manual u15947ej2v0ud 507 (4) uart communication mo de supporting handshake transfer rate: 4800 to 38400 bps figure 28-12. communication with dedi cated flash programmer (uart0 + hs) pd78f0148 v pp reset txd0 rxd0 hs v pp v dd gnd /reset si/rxd so/txd x1 clk x2 h/s dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x xxxx xxxxxx xx xx xxxx yyyy statve v dd /ev dd /av ref v ss /ev ss /av ss (5) uart6 transfer rate: 4800 to 76800 bps figure 28-13. communication with de dicated flash programmer (uart6) pd78f0148 v pp v dd v ss reset txd6 rxd6 v pp v dd gnd /reset si/rxd so/txd x1 clk x2 dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx yy y xxxxx xxxxxx xxxx xx x x y y y y statve
chapter 28 ? { { { /reset output reset signal reset si/rxd input receive signal so10/txd0/txd6 so/txd output transmit signal si10/rxd0/rxd6 sck output transfer clock sck10 { : the pin does not have to be connected if the signal is generated on the target board.
chapter 28 ?
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chapter 28 pd78f0148 user?s manual u15947ej2v0ud 514 28.7.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated flash programmer, set the pd78f0148 in the flash memory programming mode. to set the mode, set the v pp pin and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 28-19. flash memory programming mode 10.0 v v ss reset v pp v dd v pp pulse flash memory programming mode 12 n    v pp operation mode v ss normal operation mode 10.0 v flash memory programming mode 28.7.3 selecting communication mode in the pd78f0148 a communication mode is selected by inputting pulses (up to 11 pulses) to the v pp pin after the dedicated flash memory programming mode is entered. these v pp pulses are generated by the flash programmer. the following table shows the relationship between the number of pulses and communication modes. table 28-7. communication modes standard (type) setting note 1 communication mode port (comm port) speed (sio clock) on target (cpu clock) frequency (flashpro clock) multiply rate (multiple rate) pins used number of v pp pulses 3-wire serial i/o (csi10) sio-ch0 (sio ch-0) 200 k to 2 mhz note 2 so10, si10, sck10 0 3-wire serial i/o with handshake supported (csi10 + hs) sio-h/s (sio ch-3 + handshake) 200 k to 2 mhz note 2 so10, si10, sck10, hs/p15 3 uart (uart0) uart-ch0 (uart ch-0) 4800 to 38400 bps notes 2, 3 txd0, rxd0 8 uart (uart6) uart-ch1 (uart ch-1) 4800 to 76800 bps notes 2, 3 txd6, rxd6 9 uart with handshake supported (uart0 + hs) uart-ch3 (uart ch-3) 4800 to 38400 bps notes 2, 3 optional 2 m to 10 mhz 1.0 txd0, rxd0, hs/p15 11 notes 1. selection items for standard settings on flashpro iv (type settings on flashpro iii). 2. the possible setting range differs depending on the voltage. for details, refer to the chapters of electrical specifications. 3. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. caution when uart0 or uart6 is sel ected, the receive clock is calcu lated based on the reset command sent from the dedicated flash programmer after the v pp pulse has been received. remark items enclosed in parentheses in the setting item co lumn are the set value and set item when they differ from those of flashpro iv.
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user?s manual u15947ej2v0ud 516 chapter 29 instruction set this chapter lists each instruction set of the 78k0/kf1 in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 29.1 conventions used in operation list 29.1.1 operand identifiers and specification methods operands are written in the ?operand? column of each instruction in accordan ce with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. uppercase letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 517 29.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register ??
chapter 29 instruction set user?s manual u15947ej2v0ud 518 29.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 519 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 520 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 521 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 522 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 523 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 524 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 525 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 29 instruction set user?s manual u15947ej2v0ud 526 29.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except r = a
chapter 29 instruction set user?s manual u15947ej2v0ud 527 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1
chapter 29 instruction set user?s manual u15947ej2v0ud 528 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
user?s manual u15947ej2v0ud 529 chapter 30 electrical specifications (standard products, (a) grade products) target products: pd780143, 780144, 780146, 780148, 78f0148, 780143(a), 780144(a), 780146(a), 780148(a), 78f0148(a) absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v ev dd ? 0.3 to +6.5 v regc ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v ev ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0148, 78f0148(a) only, note 2 ? 0.3 to +10.5 v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p120, p140 to p145, x1, x2, xt1, xt2, reset ? 0.3 to v dd + 0.3 note 1 v n-ch open drain ? 0.3 to +13 v v i2 p62, p63 on-chip pull-up resistor ? 0.3 to v dd + 0.3 note 1 v input voltage v i3 v pp in flash programming mode ( pd78f0148, 78f0148(a) only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 10 ma p00 to p06, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p142 to p145 ? 30 ma output current, high i oh total of all pins ? 60 ma p10 to p17, p30 to p33, p120, p130, p140, p141 ? 30 ma note 1. must be 6.5 v or lower. (see note 2 on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 530 absolute maximum ratings (t a = 25 ? ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 531 x1 oscillator characteristics (t a = ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 532 ring-osc oscillator characteristics (t a = ? ? ? ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 533 recommended oscillator constants caution for the resonator selection of the ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 534 (b) ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 535 dc characteristics (1/4) (t a = ? ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 536 dc characteristics (2/4) (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 537 dc characteristics (3/4): ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 538 dc characteristics (4/4): ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 539 ac characteristics (1) basic operation (t a = ? 40 to +85 c, 2.7 v v dd = ev dd 5.5 v, 2.7 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit note 1 4.0 v v dd 5.5 v 0.238 16 s 4.0 v v dd 5.5 v 0.2 16 s 3.3 v v dd < 4.0 v 0.238 16 s x1 input clock note 2 2.7 v v dd < 3.3 v 0.4 16 s main system clock operation ring-osc clock 4.17 8.33 16.67 s instruction cycle (minimum instruction execution time) t cy subsystem clock operation 114 122 125 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 4 s ti000, ti010, ti001 note 3 , ti011 note 3 input high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 4 s 4.0 v v dd 5.5 v 10 mhz ti50, ti51 input frequency f ti5 2.7 v v dd < 4.0 v 5 mhz 4.0 v v dd 5.5 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 2.7 v v dd < 4.0 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s 4.0 v v dd 5.5 v 50 ns key return input low-level width t kr 2.7 v v dd < 4.0 v 100 ns reset low-level width t rsl 10 s notes 1. when the regc pin is connected to v ss via a capacitor (1 f: recommended). 2. when the regc pin is connected directly to v dd . 3. pd780146, 780148, 78f0148, 780146(a) , 780148(a), and 78f0148(a) only. 4. selection of f sam = f xp , f xp /4, f xp /256, or f xp , f xp /16, f xp /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode registers 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f xp.
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 540 t cy vs. v dd (x1 input clock operation) (a) when regc pin is connected to v ss via capacitor (1
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 541 (2) read/write operation (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 542 (2) read/write operation (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 543 (3) serial interface (t a = ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 544 (e) 3-wire serial i/o mode with au tomatic transmit/receive function (scka0... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v ? ? ? ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 545 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 546 reset input timing reset t rsl read/write operation external fetch (no wait): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 547 external data access (no wait): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 548 serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0:
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 549 3-wire serial i/o mode with automa tic transmit/receive function: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t byh t sps t bys 789 note 10 note 10+n note 1 scka0 busy0 (active-high) note the signal is not actually driven low here; it is shown as such to indicate the timing.
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 550 a/d converter characteristics (t a = ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 551 lvi circuit characteristics (t a = ? ?
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 552 flash memory programming characteristics: the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the issu ance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50
chapter 30 electrical specifications (standard products, (a) grade products) user?s manual u15947ej2v0ud 553 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd
user?s manual u15947ej2v0ud 554 chapter 31 electrical specifi cations ((a1) grade products) target products: pd780143(a1), 780144(a1), 780146( a1), 780148(a1), 78f0148(a1) cautions 1. be sure to connect the regc pin of (a1) grade products directly to v dd . 2. the external bus interface function cannot be used with (a1) grade products. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v ev dd ? 0.3 to +6.5 v regc ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v ev ss ? 0.3 to +0.3 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v supply voltage v pp pd78f0148(a1) only, note 2 ? 0.3 to +10.5 v v i1 p00 to p06, p10 to p17, p20 to p27, p30 to p33, p40 to p47, p50 to p57, p60, p61, p64 to p67, p70 to p77, p120, p140 to p145, x1, x2, xt1, xt2, reset ? 0.3 to v dd + 0.3 note 1 v n-ch open drain ? 0.3 to +13 v v i2 p62, p63 on-chip pull-up resistor ? 0.3 to v dd + 0.3 note 1 v input voltage v i3 v pp in flash programming mode ( pd78f0148(a1) only) ? 0.3 to +10.5 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an av ss ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v per pin ? 8 ma p00 to p06, p40 to p47, p50 to p57, p64 to p67, p70 to p77, p142 to p145 ? 24 ma output current, high i oh total of all pins ? 48 ma p10 to p17, p30 to p33, p120, p130, p140, p141 ? 24 ma note 1. must be 6.5 v or lower. (refer to note 2 on the next page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins.
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 555 absolute maximum ratings (t a = 25 ? ? in flash memory programming mode ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 556 x1 oscillator characteristics (t a = ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 557 ring-osc oscillator characteristics (t a = ? ? ? ? ? ? ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 558 dc characteristics (1/6): ? ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 559 dc characteristics (2/6): ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 560 dc characteristics (3/6): ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 561 dc characteristics (4/6): ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 562 dc characteristics (5/6): ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 563 dc characteristics (6/6): ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 564 ac characteristics (1) basic operation (t a = ? 40 to +110 c note 1 , 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.5 v v dd 5.5 v 0.2 16 s 4.0 v v dd < 4.5 v 0.238 16 s x1 input clock 3.3 v v dd < 4.0 v 0.4 16 s main system clock operation ring-osc clock 4.09 8.33 16.67 s instruction cycle (minimum instruction execution time) t cy subsystem clock operation 114 122 125 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 3 s ti000, ti010, ti001 note 2 , ti011 note 2 input high-level width, low-level width t tih0 , t til0 3.3 v v dd < 4.0 v 2/f sam + 0.2 note 3 s 4.0 v v dd 5.5 v 10 mhz ti50, ti51 input frequency f ti5 3.3 v v dd < 4.0 v 5 mhz 4.0 v v dd 5.5 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 3.3 v v dd < 4.0 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s 4.0 v v dd 5.5 v 50 ns key return input low-level width t kr 3.3 v v dd < 4.0 v 100 ns reset low-level width t rsl 10 s notes 1. t a = ? 40 to +110 c: pd780143(a1), 780144(a1), 780146(a1), 780148(a1) t a = ? 40 to +105 c: pd78f0148(a1) 2. pd780146(a1), 780148(a1), and 78f0148(a1) only. 3. selection of f sam = f xp , f xp /4, f xp /256, or f xp , f xp /16, f xp /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode registers 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f xp.
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 565 t cy vs. v dd (x1 input clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 3.3 4.5 guaranteed operation range 20.0 16.0 0.238
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 566 (2) serial interface (t a = ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 567 (e) 3-wire serial i/o mode with au tomatic transmit/receive function (scka0... internal clock output) parameter symbol conditions min. typ. max. unit 4.5 v ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 568 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 569 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0:
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 570 3-wire serial i/o mode with automa tic transmit/receive function: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t byh t sps t bys 789 note 10 note 10+n note 1 scka0 busy0 (active-high) note the signal is not actually driven low here; it is shown as such to indicate the timing.
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 571 a/d converter characteristics (t a = ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 572 lvi circuit characteristics (t a = ? ? ? ? ? ?
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 573 flash memory programming characteristics: the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 50 ms. 4. writeback is executed once by the issu ance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step write time is 50
chapter 31 electrical specifications ((a1) grade products) user?s manual u15947ej2v0ud 574 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd
user?s manual u15947ej2v0ud 575 chapter 32 electrical specifi cations ((a2) grade products) target products: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 576 absolute maximum ratings (t a = 25 ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 577 x1 oscillator characteristics (t a = ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 578 ring-osc oscillator characteristics (t a = ? ? ? ? ? ? ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 579 dc characteristics (1/3) (t a = ? ? ? ? ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 580 dc characteristics (2/3) (t a = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 581 dc characteristics (3/3) (t a = ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 582 ac characteristics (1) basic operation (t a = ? 40 to +125 c, 3.3 v v dd = ev dd 5.5 v, 3.3 v av ref v dd , v ss = ev ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.238 16 s x1 input clock 3.3 v v dd < 4.0 v 0.4 16 s main system clock operation ring-osc clock 4.04 8.33 16.67 s instruction cycle (minimum instruction execution time) t cy subsystem clock operation 114 122 125 s 4.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s ti000, ti010, ti001 note 1 , ti011 note 1 input high-level width, low-level width t tih0 , t til0 3.3 v v dd < 4.0 v 2/f sam + 0.2 note 2 s 4.0 v v dd 5.5 v 8.38 mhz ti50, ti51 input frequency f ti5 3.3 v v dd < 4.0 v 5 mhz 4.0 v v dd 5.5 v 59.6 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 3.3 v v dd < 4.0 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s 4.0 v v dd 5.5 v 59.6 ns key return input low-level width t kr 3.3 v v dd < 4.0 v 100 ns reset low-level width t rsl 10 s notes 1. pd780146(a2) and 780148(a2) only. 2. selection of f sam = f xp , f xp /4, f xp /256, or f xp , f xp /16, f xp /64 is possible using bits 0 and 1 (prm000, prm001 or prm010, prm011) of prescaler mode registers 00 and 01 (prm00, prm01). note that when selecting the ti000 or ti001 valid edge as the count clock, f sam = f xp.
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 583 t cy vs. v dd (x1 input clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 3.3 guaranteed operation range 20.0 16.0 0.238
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 584 (2) serial interface (t a = ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 585 (e) 3-wire serial i/o mode with au tomatic transmit/receive function (scka0... internal clock output) parameter symbol conditions min. typ. max. unit scka0 cycle time t kcy3 1200 ns scka0 high-/low-level width t th3 , t tl3 t kcy3 /2 ? ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 586 ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti00, ti010, ti001 note , ti011 note t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth note
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 587 reset input timing reset t rsl serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0:
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 588 3-wire serial i/o mode with automa tic transmit/receive function: stb0 scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 t sbd t sbw 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t byh t sps t bys 789 note 10 note 10+n note 1 scka0 busy0 (active-high) note the signal is not actually driven low here; it is shown as such to indicate the timing.
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 589 a/d converter characteristics (t a = ? ?
chapter 32 electrical specifications ((a2) grade products) user?s manual u15947ej2v0ud 590 lvi circuit characteristics (t a = ? ?
user?s manual u15947ej2v0ud 591 chapter 33 package drawings 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 + ?
chapter 33 package drawings user?s manual u15947ej2v0ud 592 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 + ? + ?
user?s manual u15947ej2v0ud 593 chapter 34 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 34-1. surface mounting type soldering cond itions (1/3) (1) 80-pin plastic qfp (14 14) ?
chapter 34 recommended soldering conditions user?s manual u15947ej2v0ud 594 table 34-1. surface mounting type soldering cond itions (2/3) (2) 80-pin plastic tqfp (fine pitch) (12 12) ?
chapter 34 recommended soldering conditions user?s manual u15947ej2v0ud 595 table 34-1. surface mounting type soldering cond itions (3/3) (3) 80-pin plastic tqfp (fine pitch) (12 12) , 78f0148m2gk-9eu , 78f0148m3gk-9eu, 78f0148m4gk-9eu, 78f0148m5gk-9eu , , 78f0148m1gk(a)-9eu , 78f0148m2gk(a)-9eu , 78f0148m3gk(a)-9eu , , 78f0148m5gk(a)-9eu , 78f0148m6gk(a)-9eu , 78f0148m1gk(a1)-9eu , , 78f0148m5gk(a1)-9eu , 78f0148m6gk(a1)-9eu soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 ?
user?s manual u15947ej2v0ud 596 chapter 35 cautions for wait 35.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflict s with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cp u repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instructi on processing but waits. if this happens, the number of execution clocks of an instruction incr eases by the number of wait clocks (f or the number of wait clocks, see table 35- 1 ). this must be noted when r eal-time processing is performed.
chapter 35 cautions for wait user?s manual u15947ej2v0ud 597 35.2 peripheral hardware that generates wait table 35-1 lists the register s that issue a wait request when accessed by the cpu, and the number of cpu wait clocks. table 35-1. registers that generate wait and number of cpu wait clocks peripheral hardware register a ccess number of wait clocks watchdog timer wdtm write 3 clocks (fixed) serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) adm write ads write pfm write pft write 2 to 5 clocks note (when adm.5 flag = ?1?) 2 to 9 clocks note (when adm.5 flag = ?0?) adcr read 1 to 5 clocks (when adm.5 flag = ?1?) 1 to 9 clocks (when adm.5 flag = ?0?) a/d converter {(1/f macro )
chapter 35 cautions for wait user?s manual u15947ej2v0ud 598 35.3 example of wait occurrence <1> watchdog timer number of execution clocks: 8 (5 clocks when data is written to a register that does not issue a wait (mov sfr, a).) number of execution clocks: 10 (7 clocks when data is written to a register that does not issue a wait (mov sfr, #byte).) <2> serial interface uart6 number of execution clocks: 6 (5 clocks when data is read from a register that does not issue a wait (mov a, sfr).) <3> a/d converter table 35-2. number of wait clocks and number of execution clocks on occurrence of wait (a/d converter) ?
user?s manual u15947ej2v0ud 599 appendix a development tools the following development t ools are available for the development of systems that employ the 78k0/kf1. figure a-1 shows the developm ent tool configuration. ? ? ? ? ?
appendix a development tools user?s manual u15947ej2v0ud 600 figure a-1. development tool configuration (1/2) (1) when using the in-circuit em ulators ie-78k0-ns, ie-78k0-ns-a language processing software  assembler package  c compiler package  device file  c library source file note 1 debugging software  integrated debugger  system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator note 3 emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory  software package  project manager (windows only) note 2 software package flash memory write environment control software embedded software  real-time os performance board power supply unit notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. 3. products other than in-circuit emulators ie-78k0- ns and ie-78k0-ns-a are all sold separately.
appendix a development tools user?s manual u15947ej2v0ud 601 figure a-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-78k0k1-et language processing software  assembler package  c compiler package  device file  c library source file note 1 debugging software  integrated debugger  system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator note 3 emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory  software package  project manager (windows only) note 2 software package flash memory write environment control software embedded software  real-time os power supply unit notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. 3. in-circuit emulator ie-78k0k1-et is supplied with integrated debugger id78k0-ns, a device file, power supply unit, and pci bus interface adapter ie-70000-pc i-if-a. any other products are sold separately.
appendix a development tools user?s manual u15947ej2v0ud 602 a.1 software package development tools (software) common to the 78k/0 series are combined in this package. sp78k0 78k/0 series software package part number:
appendix a development tools user?s manual u15947ej2v0ud 603 a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combi nation with a device file (df780148) (sold separately). this assembler package is a dos-based app lication. it can also be used in windows, however, by using the project manager (i ncluded in assembler package) on windows. ra78k0 assembler package part number:
appendix a development tools user?s manual u15947ej2v0ud 604 remark ? ?
appendix a development tools user?s manual u15947ej2v0ud 605 a.5 debugging tools (hardware) a.5.1 when using in-circuit emulat ors ie-78k0-ns and ie-78k0-ns-a ie-78k0-ns in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a 78k/0 series pr oduct. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-78k0-ns-pa performance board this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. ie-78k0-ns-a in-circuit emulator product that combines the ie-78k0-ns and ie-78k0-ns-pa ie-70000-mc-ps-b power supply unit this adapter is used for supplying power from a 100 v to 240 v ac outlet. ie-70000-98-if-c interface adapter this adapter is required when using a pc-980 0 series computer (except notebook type) as the host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable requi red when using a notebook-type computer as the host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the host machine. ie-780148-ns-em1 emulation board this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic tqfp (gk-9eu type). np-80gk np-h80gk-tq emulation probe tgk-080sdw conversion adapter this conversion adapter is used to conne ct the np-80gk and target system board on which an 80-pin plastic tqfp (gk-9eu type) can be mounted. this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). np-80gc emulation probe ev-9200gc-80 conversion socket this conversion socket is used to connect the np-80gc and target system board on which an 80-pin plastic qfp (g c-8bt type) can be mounted. this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). np-80gc-tq np-h80gc-tq emulation probe tgc-080sbp conversion adapter this conversion adapter is used to conne ct the np-80gc-tq or np-h80gc-tq and a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted. remarks 1. np-80gk, np-h80gk-tq, np-80g c, np-80gc-tq, and np-h80gc- tq are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgk-080sdw and tgc-080sbp are produc ts of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) 3. ev-9200gc-80 is sold in five-device units. 4. tgk-080sdw and tgc-080sbp are sold in individual units.
appendix a development tools user?s manual u15947ej2v0ud 606 a.5.2 when using in-circuit emulator ie-78k0k1-et ie-78k0k1-et notes 1, 2 in-circuit emulator the in-circuit emulator serves to d ebug hardware and software when developing application systems using a 78k0/kx1 produc t. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. ie-70000-98-if-c interface adapter this adapter is required when using a pc-980 0 series computer (except notebook type) as the host machine (c bus compatible). ie-70000-cd-if-a pc card interface this is pc card and interface cable requi red when using a notebook-type computer as the host machine (pcmcia socket compatible). ie-70000-pc-if-c interface adapter this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). ie-70000-pci-if-a interface adapter this adapter is required when using a computer with a pci bus as the host machine. this is supplied with ie-78k0k1-et. this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic tqfp (gk-9eu type). np-80gk np-h80gk-tq emulation probe tgk-080sdw conversion adapter this conversion adapter is used to conne ct the np-80gk and target system board on which an 80-pin plastic tqfp (gk-9eu type) can be mounted. this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). np-80gc emulation probe ev-9200gc-80 conversion socket this conversion socket is used to connect the np-80gc and target system board on which an 80-pin plastic qfp (g c-8bt type) can be mounted. this probe is used to connect the in-circuit emulator and target system, and is designed for an 80-pin plastic qfp (gc-8bt type). np-80gc-tq np-h80gc-tq emulation probe tgc-080sbp conversion adapter this conversion adapter is used to conne ct the np-80gc-tq or np-h80gc-tq and a target system board on which an 80-pin plastic qfp (gc-8bt type) can be mounted. notes 1. ie-78k0k1-et is supplied with a power supply unit and pci bus interface adapter ie-70000-pci-if-a. it is also supplied with integrated debugger id78k 0-ns and a device file as control software. 2. under development remarks 1. np-80gk, np-h80gk-tq, np-80g c, np-80gc-tq, and np-h80gc- tq are products of naito densei machida mfg. co., ltd. tel: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgk-080sdw and tgc-080sbp are produc ts of tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) 3. ev-9200gc-80 is sold in five-device units. 4. tgk-080sdw and tgc-080sbp are sold in individual units.
appendix a development tools user?s manual u15947ej2v0ud 607 a.6 debugging tools (software) this is a system simulator for the 78k /0 series. the sm78k0 is windows-based software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df780148) (sold separately). sm78k0 system simulator part number:
appendix a development tools user?s manual u15947ej2v0ud 608 a.7 embedded software the rx78k0 is a real-time os conforming to the ???? ???? ???? ????
user?s manual u15947ej2v0ud 609 appendix b notes on target system design the following shows a diagram of t he connection conditions between the em ulation probe and conversion adapter. design your system making allowances for conditions such as the shape of parts mount ed on the target system, as shown below. table b-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-80gc ev-9200gc-80 170 mm np-80gc-tq 170 mm np-h80gc-tq tgc-080sbp 370 mm np-80gk 170 mm np-h80gk-tq tgk-080sdw 370 mm figure b-1. distance between ie system and conversion adapter 170 mm note in-circuit emulator ie-78k0-ns, ie-78k0-ns-a, or ie-78k0k1-et emulation board ie-780148-ns-em1 conversion adapter ev-9200gc-80, tgc-080sbp, tgk-080sdw target system cn6 emulation probe np-80gc, np-80gc-tq, np-h80gc-tq, np-80gk, np-h80gk-tq note distance when using np-80gc, np -80gc-tq, and np-80gk. this is 370 mm when using np-h80gc-tq and np-h80gk-tq. remark the np-80gc, np-80gc-tq, np-h80gc-tq, np- 80gk, and np-h80gk-tq ar e products of naito densei machida mfg. co., ltd. the tgc-080sbp and tgk-080sdw are products of tokyo eletech corporation.
appendix b notes on target system design user?s manual u15947ej2v0ud 610 figure b-2. connection conditions of ta rget system (when using np-80gc-tq) emulation probe np-80gc-tq emulation board ie-780148-ns-em1 24.8 mm 25 mm 40 mm 34 mm target system conversion adapter tgc-080sbp 21 mm 21 mm 11 mm
appendix b notes on target system design user?s manual u15947ej2v0ud 611 figure b-3. connection conditions of ta rget system (when using np-h80gc-tq) emulation probe np-h80gc-tq emulation board ie-780148-ns-em1 25.3 mm 25 mm 42 mm 45 mm target system conversion adapter tgc-080sbp 21 mm 21 mm 11 mm
appendix b notes on target system design user?s manual u15947ej2v0ud 612 figure b-4. connection conditions of target system (when using np-80gk) emulation probe np-80gk emulation board ie-780148-ns-em1 23 mm 40 mm 18 mm 18 mm 34 mm target system 11 mm conversion adapter tgk-080sdw
appendix b notes on target system design user?s manual u15947ej2v0ud 613 figure b-5. connection conditions of ta rget system (when using np-h80gk-tq) emulation probe np-h80gk-tq emulation board ie-780148-ns-em1 23 mm 42 mm 45 mm target system 11 mm conversion adapter tgk-080sdw 18 mm 18 mm
user?s manual u15947ej2v0ud 614 appendix c register index c.1 register index (in alphabetical order with respect to register names) [a] a/d conversion resu lt regist er (a dcr).......................................................................................... ..............................284 a/d converter mode register (adm) .............................................................................................. ..............................281 analog input channel specification re gister (ads) .............................................................................. ........................283 asynchronous serial interface control register 6 (asi cl6) ...................................................................... ....................333 asynchronous serial interface operat ion mode regist er 0 (a sim0) ................................................................ .............303 asynchronous serial interface operat ion mode regist er 6 (a sim6) ................................................................ .............327 asynchronous serial interface recepti on error status regi ster 0 ( asis0) ........................................................ .............305 asynchronous serial interface recepti on error status regi ster 6 ( asis6) ........................................................ .............329 asynchronous serial interface transmi ssion status regi ster 6 ( asif6) ........................................................... .............330 automatic data transfer address count register 0 (adt c0)....................................................................... ..................381 automatic data transfer address point s pecification regist er 0 (a dtp0) ......................................................... ............386 automatic data transfer interval s pecification regist er 0 (adti0).............................................................. ...................388 [b] baud rate generator contro l register 0 (brg c0) ................................................................................. ........................306 baud rate generator contro l register 6 (brg c6) ................................................................................. ........................332 [c] capture/compare contro l register 00 (crc0 0).................................................................................... ........................177 capture/compare contro l register 01 (crc0 1).................................................................................... ........................177 clock monitor mode re gister (clm) .............................................................................................. ..............................470 clock output selectio n register (cks) .......................................................................................... ...............................273 clock selection regi ster 6 (c ksr6)............................................................................................. ................................331 [d] divisor selection r egister 0 (brgca0) .......................................................................................... ..............................386 [e] 8-bit timer compare re gister 50 (cr50) ......................................................................................... ..............................215 8-bit timer compare re gister 51 (cr51) ......................................................................................... ..............................215 8-bit timer coun ter 50 (t m50).................................................................................................. ....................................214 8-bit timer coun ter 51 (t m51).................................................................................................. ....................................214 8-bit timer h carrier cont rol register 1 (tmc yc1).............................................................................. ..........................238 8-bit timer h compare register 00 (cmp00)...................................................................................... ...........................233 8-bit timer h compare register 01 (cmp01)...................................................................................... ...........................233 8-bit timer h compare register 10 (cmp10)...................................................................................... ...........................233 8-bit timer h compare register 11 (cmp11)...................................................................................... ...........................233 8-bit timer h mode re gister 0 (tmhmd0) ......................................................................................... ...........................234 8-bit timer h mode re gister 1 (tmhmd1) ......................................................................................... ...........................234 8-bit timer mode contro l register 50 (tmc 50)................................................................................... ...........................218 8-bit timer mode contro l register 51 (tmc 51)................................................................................... ...........................218 external interrupt falling edg e enable regist er (egn).......................................................................... ........................437
appendix c register index user?s manual u15947ej2v0ud 615 external interrupt rising e dge enable regist er (egp)........................................................................... ........................437 [i] input switch contro l register (isc) ............................................................................................ ...................................334 internal expansion ram size switching regi ster (ixs)........................................................................... ......................497 internal memory size s witching regist er (ims) .................................................................................. ..........................496 interrupt mask flag re gister 0h (mk0h) ......................................................................................... .............................435 interrupt mask flag re gister 0l (mk0l)......................................................................................... ...............................435 interrupt mask flag re gister 1h (mk1h) ......................................................................................... .............................435 interrupt mask flag re gister 1l (mk1l)......................................................................................... ...............................435 interrupt request flag register 0h (if0h) ...................................................................................... ...............................434 interrupt request flag register 0l (if 0l) ...................................................................................... ................................434 interrupt request flag register 1h (if1h) ...................................................................................... ...............................434 interrupt request flag register 1l (if 1l) ...................................................................................... ................................434 [k] key return mode re gister (krm) ................................................................................................. ................................447 [l] low-voltage detection level selection regi ster (l vis).......................................................................... ........................483 low-voltage detecti on register (lvim) .......................................................................................... ..............................481 [m] main clock mode register (mcm) ................................................................................................. ...............................146 main osc control register (moc) ................................................................................................ ...............................147 memory expansion mo de register (mem) ........................................................................................... ........................132 memory expansion wait setting regi ster (mm) .................................................................................... ........................134 multiplication/division data r egister a0 (md a0h, md a0l) ........................................................................ ..................421 multiplication/division dat a register b0 (mdb0)................................................................................ ...........................422 multiplier/divider contro l register 0 (dm uc0) .................................................................................. ............................423 [o] oscillation stabilization time c ounter status r egister (ostc) .................................................................. ............148, 450 oscillation stabilization time select regi ster (osts).......................................................................... ..................149, 451 [p] port mode regist er 0 (p m0)..................................................................................................... .................... 123, 18 4, 366 port mode regist er 1 (p m1)................................................................................................. 123, 220, 238, 307, 334, 366 port mode regist er 12 (p m12)................................................................................................... ..................................123 port mode regist er 14 (p m14)................................................................................................... .................. 123, 27 5, 389 port mode regist er 3 (p m3)..................................................................................................... ............................123, 220 port mode regist er 4 (p m4)..................................................................................................... ....................................123 port mode regist er 5 (p m5)..................................................................................................... ....................................123 port mode regist er 6 (p m6)..................................................................................................... ....................................123 port mode regist er 7 (p m7)..................................................................................................... ....................................123 port regist er 0 (p0)........................................................................................................... ...........................................126 port regist er 1 (p1)........................................................................................................... ...........................................126 port register 12 (p12) ......................................................................................................... .........................................126 port register 13 (p13) ......................................................................................................... .........................................126
appendix c register index user?s manual u15947ej2v0ud 616 port register 14 (p14) ......................................................................................................... .........................................126 port regist er 2 (p2)........................................................................................................... ...........................................126 port regist er 3 (p3)........................................................................................................... ...........................................126 port regist er 4 (p4)........................................................................................................... ...........................................126 port regist er 5 (p5)........................................................................................................... ...........................................126 port regist er 6 (p6)........................................................................................................... ...........................................126 port regist er 7 (p7)........................................................................................................... ...........................................126 power-fail comparison mo de register (pfm) ...................................................................................... .........................285 power-fail comparison th reshold regi ster (pft) ................................................................................. .........................285 prescaler mode regi ster 00 (prm00) ............................................................................................. .............................181 prescaler mode regi ster 01 (prm01) ............................................................................................. .............................181 priority specification fl ag register 0h (p r0h) ................................................................................. .............................436 priority specification fl ag register 0l (p r0l) ................................................................................. ..............................436 priority specification fl ag register 1h (p r1h) ................................................................................. .............................436 priority specification fl ag register 1l (p r1l) ................................................................................. ..............................436 processor clock cont rol regist er (pcc) ......................................................................................... ..............................143 pull-up resistor opti on register 0 (pu0) ....................................................................................... ................................127 pull-up resistor opti on register 1 (pu1) ....................................................................................... ................................127 pull-up resistor opti on register 12 (pu 12) ..................................................................................... ..............................127 pull-up resistor opti on register 14 (pu 14) ..................................................................................... ..............................127 pull-up resistor opti on register 3 (pu3) ....................................................................................... ................................127 pull-up resistor opti on register 4 (pu4) ....................................................................................... ................................127 pull-up resistor opti on register 5 (pu5) ....................................................................................... ................................127 pull-up resistor opti on register 6 (pu6) ....................................................................................... ................................127 pull-up resistor opti on register 7 (pu7) ....................................................................................... ................................127 [r] receive buffer regi ster 0 (rxb0) ............................................................................................... .................................302 receive buffer regi ster 6 (rxb6) ............................................................................................... .................................326 remainder data regi ster 0 (sdr0)............................................................................................... ...............................420 reset control flag register (resf) ............................................................................................. .................................468 ring-osc mode r egister (rcm) ................................................................................................... ..............................145 [s] serial clock selection register 10 (csic10) .................................................................................... .............................363 serial clock selection register 11 (csic11) .................................................................................... .............................363 serial i/o shift r egister 0 (sioa0)............................................................................................ ....................................381 serial i/o shift regi ster 10 (sio10) ........................................................................................... ...................................360 serial i/o shift regi ster 11 (sio11) ........................................................................................... ...................................360 serial operation mode register 10 (csim 10) ..................................................................................... ..........................361 serial operation mode register 11 (csim 11) ..................................................................................... ..........................361 serial operation m ode specification regi ster 0 (c sima0) ........................................................................ ....................382 serial status regi ster 0 (csis0)............................................................................................... ....................................383 serial trigger regi ster 0 (csit0) .............................................................................................. ....................................385 16-bit timer capture/compar e register 000 (c r000) .............................................................................. ......................171 16-bit timer capture/compar e register 001 (c r001) .............................................................................. ......................171 16-bit timer capture/compar e register 010 (c r010) .............................................................................. ......................173 16-bit timer capture/compar e register 011 (c r011) .............................................................................. ......................173
appendix c register index user?s manual u15947ej2v0ud 617 16-bit timer count er 00 (tm00)................................................................................................. ...................................171 16-bit timer count er 01 (tm01)................................................................................................. ...................................171 16-bit timer mode contro l register 00 (tmc 00) .................................................................................. .........................174 16-bit timer mode contro l register 01 (tmc 01) .................................................................................. .........................174 16-bit timer output cont rol register 00 (t oc00)................................................................................ ...........................178 16-bit timer output cont rol register 01 (t oc01)................................................................................ ...........................178 [t] timer clock selection register 50 (tcl50) ...................................................................................... ............................216 timer clock selection register 51 (tcl51) ...................................................................................... ............................216 transmit buffer regi ster 10 (s otb10)........................................................................................... ..............................360 transmit buffer regi ster 11 (s otb11)........................................................................................... ..............................360 transmit buffer regi ster 6 (txb6).............................................................................................. ..................................326 transmit shift regi ster 0 (txs0) ............................................................................................... ...................................302 [w] watch timer operation mode register (wtm) ...................................................................................... ........................257 watchdog timer enable register (wdte) .......................................................................................... ..........................266 watchdog timer mode r egister (wdtm) ............................................................................................ .........................265
appendix c register index user?s manual u15947ej2v0ud 618 c.2 register index (in alphabetical orde r with respect to register symbol) [a] adcr: a/d conversion result regist er........................................................................................... ....................284 adm: a/d converte r mode re gister............................................................................................... ..................281 ads: analog input channel specific ation re gister............................................................................... ............283 adtc0: automatic data transfe r address count register 0 ........................................................................ .........381 adti0: automatic data transfer inte rval specificati on register 0............................................................... .........388 adtp0: automatic data transfer address point specificati on regist er 0.......................................................... ....386 asicl6: asynchronous serial in terface control register 6 ....................................................................... ............333 asif6: asynchronous serial interface transmission status register 6 ............................................................ ...330 asim0: asynchronous serial interf ace operation mode register 0 ................................................................. ....303 asim6: asynchronous serial interf ace operation mode register 6 ................................................................. ....327 asis0: asynchronous serial interface re ception error stat us regist er 0 ......................................................... ...305 asis6: asynchronous serial interface re ception error stat us regist er 6 ......................................................... ...329 [b] brgca0: divisor sele ction regi ster 0........................................................................................... .........................386 brgc0: baud rate generato r control r egister 0 .................................................................................. ................306 brgc6: baud rate generato r control r egister 6 .................................................................................. ................332 [c] cks: clock output se lection re gister........................................................................................... ...................273 cksr6: clock select ion register 6.............................................................................................. ........................331 clm: clock monito r mode re gister ............................................................................................... ..................470 cmp00: 8-bit timer h compare regi ster 00 ....................................................................................... ..................233 cmp01: 8-bit timer h compare regi ster 01 ....................................................................................... ..................233 cmp10: 8-bit timer h compare regi ster 10 ....................................................................................... ..................233 cmp11: 8-bit timer h compare regi ster 11 ....................................................................................... ..................233 cr000: 16-bit timer capture/ compare regi ster 000 ............................................................................... .............171 cr001: 16-bit timer capture/ compare regi ster 001 ............................................................................... .............171 cr010: 16-bit timer capture/ compare regi ster 010 ............................................................................... .............173 cr011: 16-bit timer capture/ compare regi ster 011 ............................................................................... .............173 cr50: 8-bit timer co mpare regi ster 50 .......................................................................................... ...................215 cr51: 8-bit timer co mpare regi ster 51 .......................................................................................... ...................215 crc00: capture/compare control regi ster 00 ..................................................................................... ...............177 crc01: capture/compare control regi ster 01 ..................................................................................... ...............177 csic10: serial clock se lection regi ster 10 ..................................................................................... .....................363 csic11: serial clock se lection regi ster 11 ..................................................................................... .....................363 csim10: serial operat ion mode regi ster 10...................................................................................... ...................361 csim11: serial operat ion mode regi ster 11...................................................................................... ...................361 csima0: serial operation mode specification register 0 ......................................................................... .............382 csis0: serial stat us register 0 ................................................................................................ ..........................383 csit0: serial trig ger regist er 0 ............................................................................................... ..........................385 [d] dmuc0: multiplier/divider control re gister 0 ................................................................................... .....................423
appendix c register index user?s manual u15947ej2v0ud 619 [e] egn: external interrupt falling edge enabl e regi ster ........................................................................... ...........437 egp: external interrupt rising edge enabl e regi ster ............................................................................ ...........437 [i] if0h: interrupt reques t flag regi ster 0h....................................................................................... ...................434 if0l: interrupt reques t flag regi ster 0l ....................................................................................... ...................434 if1h: interrupt reques t flag regi ster 1h....................................................................................... ...................434 if1l: interrupt reques t flag regi ster 1l ....................................................................................... ...................434 ims: internal memory si ze switchin g regi ster................................................................................... .............496 isc: input switch control r egist er............................................................................................. .....................334 ixs: internal expansion ram size switchin g regi ster ............................................................................ .......497 [k] krm: key return mode re gister .................................................................................................. ....................447 [l] lvim: low-voltage de tection re gister........................................................................................... ...................481 lvis: low-voltage detection level selecti on regi ster ........................................................................... ...........483 [m] mcm: main clo ck mode re gister.................................................................................................. ....................146 mda0h: multiplication/div ision data r egister a0................................................................................ ..................421 mda0l: multiplication/div ision data r egister a0................................................................................ ..................421 mdb0: multiplication/div ision data r egister b0................................................................................. .................422 mem: memory expans ion mode re gister ............................................................................................ ............132 mk0h: interrupt mask flag regist er 0h .......................................................................................... ...................435 mk0l: interrupt mask flag regist er 0l.......................................................................................... ....................435 mk1h: interrupt mask flag regist er 1h .......................................................................................... ...................435 mk1l: interrupt mask flag regist er 1l.......................................................................................... ....................435 mm: memory expansion wa it setting regist er ..................................................................................... ..........134 moc: main osc c ontrol r egister ................................................................................................. ...................147 [o] ostc: oscillation stabilization ti me counter stat us regi ster ................................................................... ..148, 450 osts: oscillation stabilizati on time select register ........................................................................... .......149, 451 [p] p0: port r egister 0............................................................................................................ ...........................126 p1: port r egister 1............................................................................................................ ...........................126 p12: port r egister 12.......................................................................................................... ...........................126 p13: port r egister 13.......................................................................................................... ...........................126 p14: port r egister 14.......................................................................................................... ...........................126 p2: port r egister 2............................................................................................................ ...........................126 p3: port r egister 3............................................................................................................ ...........................126 p4: port r egister 4............................................................................................................ ...........................126 p5: port r egister 5............................................................................................................ ...........................126 p6: port r egister 6............................................................................................................ ...........................126
appendix c register index user?s manual u15947ej2v0ud 620 p7: port r egister 7 ............................................................................................................ ...........................126 pcc: processor cloc k control register.......................................................................................... ..................143 pfm: power-fail compar ison mode regist er ....................................................................................... ............285 pft: power-fail comparis on threshol d regi ster.................................................................................. ............285 pm0: port mode register 0 ...................................................................................................... .......123, 184, 366 pm1: port mode register 1 .....................................................................................123, 220, 238, 30 7, 334, 366 pm12: port mode register 12 .................................................................................................... .......................123 pm14: port mode register 14 .................................................................................................... .......123, 275, 389 pm3: port mode register 3 ...................................................................................................... ...............123, 220 pm4: port mode register 4 ...................................................................................................... .......................123 pm5: port mode register 5 ...................................................................................................... .......................123 pm6: port mode register 6 ...................................................................................................... .......................123 pm7: port mode register 7 ...................................................................................................... .......................123 pr0h: priority specificat ion flag r egister 0h.................................................................................. ...................436 pr0l: priority specificat ion flag r egister 0l .................................................................................. ...................436 pr1h: priority specificat ion flag r egister 1h.................................................................................. ...................436 pr1l: priority specificat ion flag r egister 1l .................................................................................. ...................436 prm00: prescaler m ode register 00.............................................................................................. .....................181 prm01: prescaler m ode register 01.............................................................................................. .....................181 pu0: pull-up resistor option regi ster 0 ........................................................................................ ...................127 pu1: pull-up resistor option regi ster 1 ........................................................................................ ...................127 pu12: pull-up resistor option regi ster 12 ...................................................................................... ...................127 pu14: pull-up resistor option regi ster 14 ...................................................................................... ...................127 pu3: pull-up resistor option regi ster 3 ........................................................................................ ...................127 pu4: pull-up resistor option regi ster 4 ........................................................................................ ...................127 pu5: pull-up resistor option regi ster 5 ........................................................................................ ...................127 pu6: pull-up resistor option regi ster 6 ........................................................................................ ...................127 pu7: pull-up resistor option regi ster 7 ........................................................................................ ...................127 [r] rcm: ring-osc m ode register .................................................................................................... ..................145 resf: reset contro l flag re gister.............................................................................................. .......................468 rxb0: receive buffe r regist er 0................................................................................................ .......................302 rxb6: receive buffe r regist er 6................................................................................................ .......................326 [s] sdr0: remainder dat a regist er 0 ................................................................................................ ....................420 sio10: serial i/o sh ift register 10 ............................................................................................ .........................360 sio11: serial i/o sh ift register 11 ............................................................................................ .........................360 sioa0: serial i/o sh ift regist er 0 ............................................................................................. ..........................381 sotb10: transmit bu ffer regist er 10............................................................................................ ........................360 sotb11: transmit bu ffer regist er 11............................................................................................ ........................360 [t] tcl50: timer clock sele ction regi ster 50 ....................................................................................... ...................216 tcl51: timer clock sele ction regi ster 51 ....................................................................................... ...................216 tm00: 16-bit time r counter 00.................................................................................................. ........................171 tm01: 16-bit time r counter 01.................................................................................................. ........................171
appendix c register index user?s manual u15947ej2v0ud 621 tm50: 8-bit time r counter 50................................................................................................... .........................214 tm51: 8-bit time r counter 51................................................................................................... .........................214 tmc00: 16-bit timer mode control regi ster 00 ................................................................................... .................174 tmc01: 16-bit timer mode control regi ster 01 ................................................................................... .................174 tmc50: 8-bit timer mode control re gister 50 .................................................................................... ..................218 tmc51: 8-bit timer mode control re gister 51 .................................................................................... ..................218 tmcyc1: 8-bit timer h carri er control r egister 1 ............................................................................... ....................238 tmhmd0: 8-bit timer h mode regi ster 0 .......................................................................................... ......................234 tmhmd1: 8-bit timer h mode regi ster 1 .......................................................................................... ......................234 toc00: 16-bit timer output control re gister 00 ................................................................................. ..................178 toc01: 16-bit timer output control re gister 01 ................................................................................. ..................178 txb6: transmit buffe r register 6 ............................................................................................... ......................326 txs0: transmit shi ft register 0 ................................................................................................ ........................302 [w] wdte: watchdog timer enable re gister........................................................................................... .................266 wdtm: watchdog time r mode r egist er ............................................................................................. ................265 wtm: watch timer oper ation mode regist er ....................................................................................... ............257
user?s manual u15947ej2v0ud 622 appendix d revision history the following table shows the revision history up to this edit ion. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/5) edition description applied to: modification of reset value of the following registers in table 3-5 special function register list  serial i/o shift register 10 (sio10)  serial i/o shift register 11 (sio11)  interrupt mask flag register 1h (mk1h) modification of manipulatable bit uni t of the following register in table 3-5 special function register list  oscillation stabilization time counter status register (ostc) chapter 3 cpu architecture modification of manipulatable bi t unit and clear condition in 6.3 (5) oscillation stabilization time counter status register (ostc) modification of figure 6-13 status transition diagram modification of table 6-4 oscillation control flags and clock oscillation status chapter 6 clock generator modification of reset value in 7.2 (2) 16-bit timer capture/compare register 00n (cr00n) and (3) 16-bit timer capture/compare register 01n (cr01n) modification of mani pulatable bit unit in 7.3 (4) prescaler mode register 0n (prm0n) chapter 7 16-bit timer/event counters 00 and 01 addition of caution description in 13.6 (10) a/d conversion r esult register (adcr) read operation chapter 13 a/d converter modification of reset value in 16.2 (2) serial i/o shift register 1n (sio1n) chapter 16 serial interfaces csi10 and csi11 modification of reset value in 19.3 (2) interrupt mask flag register (mk1h) chapter 19 interrupt functions modification of manipulatable bi t unit and clear condition in 21.1.2 (1) oscillation stabilization time counter status register (ostc) modification of a/d converter item in table 21-2 operating statuses in halt mode chapter 21 standby function modification of stop conditi on of clock monitor in 23.1 functions of clock monitor and 23.4 operation of clock monitor chapter 23 clock monitor addition of 24.4 cautions for power-on-clear circuit chapter 24 power- on-clear circuit modification of figure 25-3 format of low-vo ltage detection level selection register (lvis) addition of 25.5 cautions for low-voltage detector chapter 25 low- voltage detector 1st edition (modified version) modification of description in 26.1 outline of regulator chapter 26 regulator
appendix d revision history user?s manual u15947ej2v0ud 623 (2/5) edition description applied to: modification of the following contents in chapter 30 electrical specifications (target values) ? absolute maximum ratings  x1 oscillator characteristics  subsystem clock oscillator characteristics  dc characteristics  a/d converter characteristics  poc circuit characteristics  lvi circuit characteristics  data memory stop mode low supply voltage data retention characteristics (deletion of data retention supply current)  deletion of ring-osc characteristics  flash memory programming characteristics chapter 30 electrical specifications (target values) 1st edition (modified version) modification from chapter 32 retry to chapter 32 cautions for wait chapter 32 cautions for wait addition of products ? ? ? ? ?
appendix d revision history user?s manual u15947ej2v0ud 624 (3/5) edition description applied to: deletion of input switch control register (isc ) from and addition of port registers (p0 to p7, p12 to p14) to 4.3 registers controlling port function modification of setting of output latch of p40 to p47, p50 to p57, p64, p65, and p67 in and addition of note 2 to table 4-5 settings of port mode register and output latch when using alternate function partial modification of descriptions in 4.4.1 (1) output mode , 4.4.3 (1) output mode , and (2) input mode chapter 4 port functions addition of caution to 5.1 external bus interface addition of note to figure 5-2 format of memory expansion mode register (mem) addition of caution 2 to figure 5-4 format of memory expansion wait setting register (mm) addition of remark to figure 5-8 external memory read modify write timing chapter 5 external bus interface modification of figure 6-1 block diagram of clock generator addition of note to 6.3 (1) processor clock control register (pcc) addition of cautions 2 and 3 to figure 6-6 format of oscillation stabilization time counter status register (ostc) modification of figure 6-8 examples of external circuit of x1 oscillator, figure 6-9 examples of external circuit of subsystem clock oscillator, and figure 6-10 examples of incorrect resonator connection modification of notes 4 and 5 in figure 6-13 status transition diagram (2) modification of note 4 and illustration in figure 6-13 status transition diagram (4) modification of table 6-3 relationship between operation clocks in each operation status modification of note in figure 6-14 switching from ring-osc clock to x1 input clock (flowchart) addition of note to figure 6-16 switching from x1 input clock to subsystem clock (flowchart) chapter 6 clock generator revision of chapter 7 16-bit timer/event counters 00 and 01 chapter 7 16-bit timer/event counters 00 and 01 revision of chapter 8 8-bit timer/event counters 50 and 51 chapter 8 8-bit timer/event counters 50 and 51 revision of chapter 9 8-bit timers h0 and h1 chapter 9 8-bit timers h0 and h1 modification of figure 10-1 watch timer block diagram addition of figure 10-4 example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) chapter 10 watch timer modification of figure 12-1 block diagram of clock output/buzzer output controller chapter 12 clock output/buzzer output controller revision of chapter 13 a/d converter chapter 13 a/d converter 2nd edition revision of chapter 14 serial interface uart0 chapter 14 serial interface uart0
appendix d revision history user?s manual u15947ej2v0ud 625 (4/5) edition description applied to: revision of chapter 15 serial interface uart6 chapter 15 serial interface uart6 revision of chapter 16 serial interfaces csi10 and csi11 chapter 16 serial interfaces csi10 and csi11 revision of chapter 17 serial interface csia0 chapter 17 serial interface csia0 revision of chapter 18 multiplier/divider chapter 18 multiplier/divider addition of note to intvli, poc, and lvi in table 19-1 interrupt source list addition of note 2 to table 19-2 flags corresponding to interrupt request sources addition of caution 2 to figure 19-2 format of interrupt request flag registers (if0l, if0h, if1l, if1h) addition of caution to table 19-3 ports corresponding to egpn and egnn addition of software interrupt request item to table 19-5 relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing chapter 19 interrupt functions modification of figure 20-1 block diagram of key interrupt chapter 20 key interrupt function modification of table 21-1 relationship between halt mode, stop mode, and clock in old edition to table 21-1 relationship between operation clocks in each operation status addition of cautions 2 and 3 to figure 21-1 format of oscillation stabilization time counter status register (ostc) modification of table 21-1 operating statuses in halt mode addition of (3) when subsystem clock is used as cpu clock to figure 21-4 halt mode release by reset input modification of the following items in table 21-4 operating statuses in stop mode ? ?
appendix d revision history user?s manual u15947ej2v0ud 626 (5/5) edition description applied to: modification of note 5 in figure 25-2 format of low-voltage detection register (lvim) addition of note 2 and caution to figure 25-3 format of low-voltage detection level selection register (lvis) modification of figure 25-4 timing of low-voltage detector internal reset signal generation and figure 25-5 timing of low-voltage detector interrupt signal generation partial modification of description of (2) when used as interrupt under in 25.5 cautions for low-voltage detector chapter 25 low- voltage detector revision of chapter 26 regulator chapter 26 regulator addition of note to chapter 27 mask options chapter 27 mask options revision of chapter 28


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